Showing papers by "Luca Sterpone published in 2005"

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

Abstract: Triple modular redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can generate an error in the output This paper investigates the optimal design of the TMR logic (eg, by cleverly inserting voters) to ensure robustness Four different versions of a TMR digital filter were analyzed by fault injection Faults were randomly inserted straight into the bitstream of the FPGA The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 403% to 098% the number of upsets in the routing able to cause an error in the TMR circuit

Analysis of the robustness of the TMR architecture in SRAM-based FPGAs

Abstract: Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory and thus suitable hardening techniques are needed when they are intended to be deployed in critical applications. Triple Module Redundancy is a known solution for hardening digital logic against SEUs that is widely adopted for traditional techniques (like ASICs). In this paper we present an analysis of the SEU effects in circuits hardened according to the Triple Module Redundancy to investigate the possibilities of successfully applying TMR to designs mapped on commercial-off-the-shelf SRAM-based FPGAs, which are not radiation hardened. We performed different fault-injection experiments in the FPGA configuration memory implementing TMR designs and we observed that the percentage of SEUs escaping TMR could reach 13%. In this paper we report detailed evaluations of the effects of the observed failure rates, and we proposed a first step toward an improved TMR implementation.

A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs

Abstract: In order to deploy successfully commercially-off-the-shelf SRAM-based FPGA devices in safety- or mission-critical applications, designers need to adopt suitable hardening techniques, as well as methods for validating the correctness of the obtained designs, as far as the system's dependability is concerned. In this paper we describe a new analytical approach to estimate the dependability of TMR designs implemented on SRAM-based FPGAs that, by exploiting a detailed knowledge of FPGAs architectures and configuration memory, is able to predict the effects of single event upsets with the same accuracy of fault injection but at a fraction of the fault-injection's execution time.

Multiple errors produced by single upsets in FPGA configuration memory: a possible solution

Abstract: The very high integration levels reached by SRAM-based field programmable gate arrays (FPGAs) lead to high occurrence rate of single event upsets (SEUs) in their configuration memory, which can produce multiple errors affecting routing resources. Based on detailed analysis of this phenomenon, we devised a reliability-oriented place and route algorithm able to significantly improve the reliability of SRAM-based FPGAs with limited costs in terms of performance degradation and resource occupation. To evaluate the effectiveness of the algorithm we performed extensive fault injection experiments.

Efficient estimation of SEU effects in SRAM-based FPGAs

Abstract: SRAM-based FPGAs are becoming very appealing for several applications where high dependability is a mandatory requirement. Unfortunately, the technology of SRAM-based FPGAs is very sensitive to single event upsets (SEUs) and particular concerns arise from SEUs affecting the FPGAs' configuration memory. In this paper we propose a new method for assessing the impact of faults in the configuration memory on the FPGA dependability. The method uses static analysis, thus reducing greatly the time for performing dependability evaluation.

RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs

Abstract: SRAM-based FPGA designs are extremely susceptible to single event upset (SEUs). Since the configuration memory defines which is the circuit an SRAM-based field programmable gate array (FPGA) implements, any change induced by SEUs in the configuration memory may modify drastically the implemented circuit. When such devices are used in safety-critical applications, fault tolerant techniques are needed able to mitigate the effects of SEUs in FPGA's configuration memory. In this paper we present a reliability-oriented place and route algorithm that is able to mitigate the effects of the considered upsets.

A design flow for protecting FPGA-based systems against single event upsets

Abstract: SRAM-based field programmable gate arrays (FPGAs) are very susceptible to single event upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper, we present a design flow composed by both standard tools, and ad-hoc developed tools, which designers can use fruitfully for developing circuits resilient to SEUs. Experiments are reported on both benchmarks circuits and on a realistic circuit to show the capabilities of the proposed design flow.

New evolutionary techniques for test-program generation for complex microprocessor cores

Abstract: Checking if microprocessor cores are fully functional at the end of the productive process has become a major issue. Traditional functional approaches are not sufficient when considering modern designs. This paper describes new improvements for an existing evolutionary algorithm, called µGP, able to generate Turing-complete programs; these are exploited, along with hardware acceleration techniques, to add content to a qualifying test campaign by automatically generating assembly programs. The approach is suitable for medium-sized processor cores. The experimental evaluation performed on a SPARCv8 clearly shows the potentiality of the approach, and the effectiveness of the enhancements to the evolutionary core.

An experimental analysis of hardening techniques for SRAM-based FPGAs

Abstract: Triple modular redundancy (TMR) is recognized as one of the possible solutions to harden circuits implemented on SRAM-based FPGAs against soft-errors affecting configuration memory and user memory. Several works already showed cross-section figures confirming the soundness of TMR principle, however some faults still escape the TMR's fault masking mechanism. In this work we analyzed by means of extensive fault-injection experiments the TMR architecture. We identified some of the causes that are responsible for the escaped faults, and we proposed some possible solutions. In our analyses we considered both the TMR and one of its enhanced versions, the XTMR.