Showing papers by "Luca Sterpone published in 2006"

A new reliability-oriented place and route algorithm for SRAM-based FPGAs

Abstract: The very high integration levels reached by VLSI technologies for SRAM-based field programmable gate arrays (FPGAs) lead to high occurrence-rate of transient faults induced by single event upsets (SEUs) in FPGAs' configuration memory. Since the configuration memory defines which circuit an SRAM-based FPGA implements, any modification induced by SEUs may dramatically change the implemented circuit. When such devices are used in safety-critical applications, fault-tolerant techniques are needed to mitigate the effects of SEUs in FPGAs' configuration memory. In this paper, we analyze the effects induced by the SEUs in the configuration memory of SRAM-based FPGAs. The reported analysis outlines that SEUs in the FPGA's configuration memory are particularly critical since they are able to escape well-known fault masking techniques such as triple modular redundancy (TMR). We then present a reliability-oriented place and route algorithm that, coupled with TMR, is able to effectively mitigate the effects of the considered faults. The effectiveness of the new reliability-oriented place and route algorithm is demonstrated by extensive fault injection experiments showing that the capability of tolerating SEU effects in the FPGA's configuration memory increases up to 85 times with respect to a standard TMR design technique

An Analysis Based on Fault Injection of Hardening Techniques for SRAM-Based FPGAs

Abstract: Triple Modular Redundancy (TMR) is recognized as one of the possible solutions to harden circuits implemented on SRAM-based FPGAs against soft-errors affecting configuration memory and user memory. Several works already showed cross-section figures confirming the soundness of TMR principle, however some faults still escape the TMR's fault masking mechanism. In this work we analyzed by means of extensive fault-injection experiments the TMR architecture. We identified some of the causes that are responsible for the escaped faults, and we proposed possible solutions. In our analyses we considered both the TMR and one of its enhanced version, the XTMR

A new approach to compress the configuration information of programmable devices

Abstract: During the last decade programmable devices have gained an impressive diffusion, tackling some traditional ASIC marked domains. In particular, multi-million gates FPGAs have become a very appealing low-cost solution even for consumer applications. However, one of the big issues that can arise with modern FPGA devices is the need for large and expensive external non-volatile memory to keep the configuration data. In this work we developed an alternative technique to compress FPGA bitstreams based on the knowledge of the device internal structure. The proposed method performs a two-step coder: in the first step the bitstream is adoptively "filtered" to remove data redundancy, while in the second step an arithmetic coder is used to actually compress the information. The effectiveness of the proposed technique has been demonstrated on a set of case studies. As a result conventional approaches are outperformed reaching a compression ratio of 4.26 against 3.3 times.

Fault Injection-based Reliability Evaluation of SoPCs

Abstract: Systems-on-Programmable-Chip (SoPCs) include processors, memories and programmable logic that allow to catch multiple application requirements such as high performance, reconfigurability and low-costs. Due to these characteristics, they are also becoming very attractive for safety-critical applications. However, the issue of assessing the reliability they can provide and debugging the possible safety-related mechanisms they embed is still open. In this paper, we present a new fault-injection approach for evaluating the impact of transient faults in SoPCs. Fault-injection experiments are reported on a case study consisting of a web server implemented on a Xilinx Virtex-II FPGA embedding a PowerPC 405 and running the whole TCP/IP stack.

Hybrid Fault Detection Technique: A Case Study on Virtex-II Pro's PowerPC 405

Abstract: Hardening processor-based systems against transient faults requires new techniques able to combine high fault detection capabilities with the usual design requirements, e.g., reduced design-time, low area overhead, reduced (or null) accessibility to processor internal hardware. This paper proposes the adoption of a hybrid approach, which combines ideas from previous techniques based on software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads, to harden system based on the PowerPC 405 core available in Virtex-II Pro FPGAs. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results including comparisons with previous approaches are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory and performance overheads

Combined software and hardware techniques for the design of reliable IP processors

Abstract: In the recent years both software and hardware techniques have been adopted to carry out reliable designs, aimed at autonomously detecting the occurrence of faults, to allow discarding erroneous data and possibly performing the recovery of the system. The aim of this paper is the introduction of a combined use of software and hardware approaches to achieve a complete fault coverage in generic IP processors, with respect to SEU faults. Software techniques are preferably adopted to reduce the necessity and costs of modifying the processor architecture; since a complete fault coverage cannot be achieved, partial hardware redundancy techniques are then introduced to deal with the remaining, not covered, faults. The paper presents the methodological approach adopted to achieve the complete fault coverage, the proposed resulting architecture, and the experimental results gathered from the fault injection analysis campaign.

Hardening FPGA-based systems against SEUs: A new design methodology

Abstract: SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper we present a design flow composed by both standard tools, and ad-hoc developed tools, which designers can use fruitfully for developing circuits resilient to SEUs. Experiments are reported on both benchmarkscircuits and on a realistic circuit to show the capabilities of the proposed design flow.

ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications

Abstract: Reconfigurable mixed grain (ReCoM) is a novel reconfigurable compute fabric (RCF) architecture based on a mixed-grain reconfigurable array which combines a RISC microprocessor and a reconfigurable hardware for computation-intensive applications. ReCoM comprises a modified RISC microprocessor, a dynamically reconfigurable processing array including reconfigurable cells formed by a 64-bits ALU, look up tables (LUTs), word-level arithmetic units, and an efficient configuration and data memory architecture. This paper describes the ReCoM architecture and presents its effectiveness for a digital signal processing benchmark application

An experimental analysis of a new mixed grain-based dynamically reconfigurable architecture

Abstract: This paper presents an experimental analysis of ReCoM, a novel reconfigurable architecture based on a mixed-grain reconfigurable array that combines a RISC microprocessor and a dynamically-configurable hardware for computation-intensive applications. The reconfigurable hardware is composed by mixed-grain reconfigurable cells that include 64-bits ALU, Look-Up Tables (LUTs), word-level arithmetic units and an efficient configuration and data memory architecture. To study the effectiveness of ReCoM on a well-known reference application, we implemented several FIR filters. The experimental results gathered through an accurate simulation model of ReCoM show performance figures encouragingly better than other DSP or alternative reconfigurable systems. Moreover, they demonstrate that ReCoM is very scalable and it successfully extracts the parallelism from streamed applications.

Dependability evaluation of transient fault effects in reconfigurable compute fabric devices

Abstract: Reconfigurable compute fabrics (RCFs) are cellular architectures in which an array of computing elements and a configurable interconnection fabric are combined with a general-purpose processor. RCFs can play an important role in safety- or mission-critical applications, provided that a clear understanding of their dependability is available. In this paper, we report an evaluation of the effects induced by transient faults within the resources of an RCF Motorola MRC6011 and we resorted to extensive fault injection to investigate the effects of transient faults.