Showing papers by "Luca Sterpone published in 2009"
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TL;DR: A non invasive approach for the implementation of fault tolerant systems based on COTS processors embedded in FPGAs, using lockstep in conjunction with checkpoint and rollback recovery, is presented.
Abstract: The growing availability of embedded processors inside FPGAs provides unprecedented flexibility for system designers. The use of such devices for space or mission critical applications, however, is being delayed by the lack of effective low cost techniques to mitigate radiation induced errors. In this paper a non invasive approach for the implementation of fault tolerant systems based on COTS processors embedded in FPGAs, using lockstep in conjunction with checkpoint and rollback recovery, is presented. The proposed approach does not require modifications in the processor architecture or in the application software. The experimental validation of this approach through fault injection is described, the corresponding results are discussed, and the addition of a write history table as a means to reduce the performance overhead imposed by previous implementations is proposed and evaluated.
45 citations
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01 Sep 2009TL;DR: A technique based on electrical pulse injection for the analysis of SETs propagation within logic resources of Flash-based FPGAs is developed, providing detailed characterization of basic gates and realistic routing and logic paths.
Abstract: Advanced digital circuits are increasingly sensitive to single event transients (SETs) phenomena. Technology scaling has resulted in a greater sensitivity to single event effects (SEEs) and more in particular to SET propagation, since transients may be generated and propagated through the circuit logic, leading to behavioral errors of the affected circuit. When circuits are implemented on Flash-based FPGAs, SETs generated in the combinational logic resources are the main source of critical behavior. In this paper, we developed a technique based on electrical pulse injection for the analysis of SETs propagation within logic resources of Flash-based FPGAs. We outline logic schematic that allows the injection of different SET pulses. We performed several experimental analyses. We characterized the basic logic gates used by circuits implemented on Flash-based FPGAs evaluating the effect on logic-chains of real lengths. Additionally, we performed an effective analysis evaluating the SET propagation through microprocessor logic paths. Results demonstrated the possibility of mitigating SET-broadening effects by acting on physical place and route constraints.
33 citations
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TL;DR: This paper outlines different methodologies that can be used in order to characterize SEE sensitivity, using both heavy-ions radiation experiments and analytical approaches, and details the contributions of different SEEs as a function of operating frequency and routing on a realistic circuit.
Abstract: Flash-based FPGAs are more and more interesting for space applications because of their robustness against Single Event Upsets (SEUs) in configuration memory. However, as Single Event Effects (SEEs) are still a concern both for user memory and the configurable logic, accurate evaluations are needed to identify mitigation techniques for securing their use in space missions. In this paper the SEE sensitivity of circuits implemented in Flash-based FPGAs is evaluated with respect to the working frequency and different routing schemes. We outline different methodologies that can be used in order to characterize SEE sensitivity, using both heavy-ions radiation experiments and analytical approaches. Experimental results detail the contributions of different SEEs as a function of operating frequency and routing on a realistic circuit.
17 citations
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20 Apr 2009TL;DR: A new methodology to identify the most critical switches inside the configuration logic block and the most redundant and robust configuration selection for each logic function is proposed and it is shown that by using the most robust functional mapping it is possible to enhance the reliability of the entire design with respect to a not robust ones.
Abstract: Flash-based FPGAs are increasingly demanded in safety critical fields, in particular space and avionic ones, due to their non-volatile configuration memory. Although they are almost immune to permanent loss of the configuration data, they are composed of floating gate based switches that can suffer transient effects if hit by high energetic particles with critical consequences on the implemented logic. This paper presents a new way for the analysis of the impact of Single Event Effects in Flash-based FPGAs. We proposed a new methodology to identify the most critical switches inside the configuration logic block and the most redundant and robust configuration selection for each logic function. The experimental results achieved by fault injection demonstrated the feasibility of the proposed method and show that by using the most robust functional mapping it is possible to enhance the reliability of the entire design with respect to a not robust ones.
9 citations
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01 Sep 2009
TL;DR: This paper presents a methodology suitable for analyzing the sensitivity of circuits implemented in SRAM-based FPGAs, and adopting the TMR mitigation scheme, and reports data focusing on a Virtex-II device showing the capabilities of the proposed method.
Abstract: Multiple Cell Upsets (MCUs) are becoming a growing concern with the advent of the newest FPGA devices. In this paper we present a methodology suitable for analyzing the sensitivity of circuits implemented in SRAM-based FPGAs, and adopting the TMR mitigation scheme. Data about the layout of the adopted FPGA are obtained by means of laser testing. Then static analysis algorithm uses the collected data to predict the impact of MCUs on designs implemented on SRAM-based FPGAs. Thanks to this approach MCUs affecting physically adjacent cells are considered, only. We report data focusing on a Virtex-II device, showing the capabilities of the proposed method.
9 citations
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TL;DR: The effectiveness of the novel dual-core architecture is demonstrated by several analyses performed on original DNA microarray images, showing that the capability of detecting DNA spots increases by more than the 30% with respect to that of previously developed software techniques.
Abstract: A deoxyribonucleic acid (DNA) microarray is a collection of microscopic DNA spots attached to a solid surface, such as a glass, plastic, or silicon chip forming an array. DNA microarray technologies are an essential part of modern biomedical research. DNA microarray allows compressing hundreds of thousands of different DNA nucleotide sequences in a little microscope glass and permits having all this information on a single image. The analysis of DNA microarray images allows the identification of gene expressions to draw biological conclusions for applications ranging from genetic profiling to diagnosis of cancer. Unfortunately, DNA microarray technology has a high variation of data quality. Therefore, to obtain reliable results, complex and extensive image analysis algorithms should be applied before the actual DNA microarray information can be used for biomedical purposes. In this paper, we present a novel hardware architecture that is specifically designed to analyze DNA microarray images. The architecture is based on a dual-core system that implements several units working in a single-instruction/multiple-data fashion. A field-programmable-gate-array (FPGA)-based prototypal implementation of the proposed architecture is presented. The effectiveness of the novel dual-core architecture is demonstrated by several analyses performed on original DNA microarray images, showing that the capability of detecting DNA spots increases by more than the 30% with respect to that of previously developed software techniques.
7 citations
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29 Sep 2009TL;DR: Reconfigurable platforms are getting more and more interesting for space applications due to their flexibility and low cost, along with high performance and low power dissipation that new devices provide, however, space environment is rich in radiation that can induce soft errors in electronic parts.
Abstract: Reconfigurable platforms are getting more and more interesting for space applications due to their flexibility and low cost, along with high performance and low power dissipation that new devices provide. However, space environment is rich in radiation that can induce soft errors in electronic parts. Last years have been characterized by the increase of interest in Commercial-Off-The-Shelf COTS) FPGAs with respect to radiation hardened ones, because of their higher performance and the cost of the latter, one or two order of magnitude higher. However, electronic devices operating in space live in a harsh environment characterized by high charged particles such as heavy ions, which can induce modifications in the correct circuit behavior (soft errors) leading to failures. Radiation has two major effects on such devices: Single Event Effects (SEEs), soft errors caused by a single particle, and Total Ionizing Dose (TID), the effect of radiation accumulation.
4 citations
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07 Mar 2009TL;DR: A new timing-driven placement algorithm is proposed for implementing soft-errors resilient circuits on SRAM-based FPGAs with a negligible degradation of performance based on a placement heuristic able to remove the crossing error domains while decreasing the routing congestions and delay inserted by the TMR routing and voting scheme.
Abstract: Electronic systems for safety critical applications such as space and avionics need the maximum level of dependability for guarantee the success of their missions. Contrariwise the computation capabilities required in these fields are constantly increasing for afford the implementation of different kind of applications ranging from the signal processing to the networking. SRAM-based FPGA is the candidate device for achieve this goal thanks to their high versatility of implementing complex circuits with a very short development time. However, in critical environments, the presence of Single Event Upsets (SEUs) affecting the FPGA's functionalities, requires the adoption of specific fault tolerant techniques, like Triple Modular Redundancy (TMR), able to increase the protection capability against radiation effects, but on the other side, introducing a dramatic penalty in terms of performances. In this paper, it is proposed a new timing-driven placement algorithm for implementing soft-errors resilient circuits on SRAM-based FPGAs with a negligible degradation of performance. The algorithm is based on a placement heuristic able to remove the crossing error domains while decreasing the routing congestions and delay inserted by the TMR routing and voting scheme. Experimental analysis performed by timing analysis and SEU static analysis point out a performance improvement of 29% on the average with respect to standard TMR approach and an increased robustness against SEU affecting the FPGA's configuration memory.
4 citations
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01 Dec 2009TL;DR: This paper presents the design of a new Reconfigurable Cell (RC) based on a mixed-grain architecture that delivers a gate-level implementation of the Reconfigured Logic Unit (RLU) focusing on the ALU implementation.
Abstract: Reconfigurable mixed grain architectures have been demonstrated to be efficient and flexible for data parallel and computation-intensive applications. In this paper we present the design of a new Reconfigurable Cell (RC) based on a mixed-grain architecture. The architecture delivers a gate-level implementation of the Reconfigurable Logic Unit (RLU) focusing on the ALU implementation. The investigation of the new reconfigurable cell has been performed on 0.35, 0.25 and 0.18 micron CMOS technology. Experimental results include synthesis implementation and optimization data as well as performances analysis performed on some benchmark applications. On the average ReCoM results more than 6 times better performant than alternative reconfigurable architecture.
1 citations
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16 Mar 2009TL;DR: A survey of the CAD tools for the programmable devices design phases is presented exploring the variety and particularity offered and analyzing the most influcnt results achieved on this area.
Abstract: Reconfigurable logic devices such as field programmable logic arrays (FPGAs) or programmable array logics are nowadays introducing a new design paradigm over the possible techniques an electronic or computing designer may choose to make the desired hardware chip running. Thanks to the higher design flexibility and the increasing performances supported by these devices on several aspects such as power, frequency, and dependability, programmable logic devices design tools play a central rule among the computer aided design (CAD) tools available. The basic concept behind this success is the possibility of defining the logic functionality of an electronic circuits without having a direct interface with the silicon layout mask of the chip itself. FPGA CAD tools have an increasing impact on the performances offered by current programmable devices. state-of-the-art CAD tools support both the synthesis of optimized logic functions and the implementation of design referring to the manner in which programmable switches and hard-wired interconnections are placed between logic functions. In this article survey of the CAD tools for the programmable devices design phases is presented exploring the variety and particularity offered and analyzing the most influcnt results achieved on this area.
Keywords:
FPGA;
PAL;
implementation;
synthesis;
place and route;
optimization;
dependability
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29 May 2009TL;DR: A new method for estimate the quality degree and the data's reliability of a microarray analysis is presented and the efficiency of the proposed approach in terms of genes expression classification has been demonstrated through a clustering supervised analysis performed on a set of three different histological samples related to the Lymphoma's cancer disease.
Abstract: Gene expression is the fundamental control of the structure and functions of the cellular versatility and adaptability of any organisms. The measurement of gene expressions is performed on images generated by optical inspection of microarray devices which allow the simultaneous analysis of thousands of genes. The images produced by these devices are used to calculate the expression levels of mRNA in order to draw diagnostic information related to human disease. The quality measures are mandatory in genes classification and in the decision-making diagnostic. However, microarrays are characterized by imperfections due to sample contaminations, scratches, precipitation or imperfect gridding and spot detection. The automatic and efficient quality measurement of microarray is needed in order to discriminate faulty gene expression levels. In this paper we present a new method for estimate the quality degree and the data's reliability of a microarray analysis. The efficiency of the proposed approach in terms of genes expression classification has been demonstrated through a clustering supervised analysis performed on a set of three different histological samples related to the Lymphoma's cancer disease.