Showing papers by "Luca Sterpone published in 2012"

Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs

Abstract: SRAM-based FPGAs are more and more relevant in a growing number of applications, ranging from the automotive to the aerospace ones. Designers of safety-critical applications demand accurate methodologies to evaluate the Single Event Upsets (SEUs) sensitivity of their designs. In this paper, we present an accurate simulation method for the evaluation of the effects of SEUs in the configuration memory of SRAM-based FPGAs. The approach is able to simulate SEUs affecting the configuration memory of both logic and routing resources since it is able to accurately model the electrical behavior of SEUs in the configuration memory. Detailed experimental results on a large set of benchmark circuits are provided and the comparison with fault injection experiments is shown in order to validate the accuracy of the proposed method. The results clearly demonstrate the benefits of our approach since simulation results predict almost completely the results obtained through fault injection.

A new SBST algorithm for testing the register file of VLIW processors

Abstract: Feature size reduction drastically influences permanent faults occurrence in nanometer technology devices. Among the various test techniques, Software-Based Self-Test (SBST) approaches have been demonstrated to be an effective solution for detecting logic defects, although achieving complete fault coverage is a challenging issue due to the functional-based nature of this methodology. When VLIW processors are considered, standard processor-oriented SBST approaches result deficient since not able to cope with most of the failures affecting VLIW multiple parallel domains. In this paper we present a novel SBST algorithm specifically oriented to test the register files of VLIW processors. In particular, our algorithm addresses the cross-bar switch architecture of the VLIW register file by completely covering the intrinsic faults generated between the multiple computational domains. Fault simulation campaigns comparing previously developed methods with our solution demonstrate its effectiveness. The results show that the developed algorithm achieves a 97.12% fault coverage which is about twice better than previously developed SBST algorithms. Further advantages of our solution are the limited overhead in terms of execution cycles and memory occupation.

A scalable platform for run-time reconfigurable satellite payload processing

Abstract: Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today's FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance increase, for improving energy efficiency, and for enhanced fault tolerance. To be able to prove the effectiveness of these novel approaches for satellite payload processing, a highly scalable prototyping environment has been developed, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. Up to 30 SpaceWire interfaces, 5 copper-based SpaceFibre interfaces, and 270 GPIOs can be realized and combined with one to five dynamically reconfigurable Xilinx FPGAs and up to 20 GByte of working memory. The implemented approach for dynamic reconfiguration enables partial reconfiguration at 400 MByte/s. Blind and readback scrubbing is supported and the scrub rate can be adapted individually for different parts of the design.

On the development of Software-Based Self-Test methods for VLIW processors

Abstract: Software-Based Self-Test (SBST) approaches are an effective solution for detecting permanent faults; this technique has been widely used with a good success on generic processors and processors-based architectures; however, when VLIW processors are addressed, traditional SBST techniques and algorithms must be adapted to each particular VLIW architecture. In this paper, we present a method that formalizes the development flow to write effective SBST programs for VLIW processors, starting from known algorithms addressing traditional processors. In particular, the method addresses the parallel Functional Units, such as ALUs and MULs, embedded into a VLIW processor. Fault simulation campaigns confirm the validity of the proposed method.

On the optimized generation of Software-Based Self-Test programs for VLIW processors

Abstract: Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this paper we present a new method that, starting from previously known algorithms, automatically generates an effective test program able to still reach high fault coverage on the VLIW processor under test, while reducing the test duration and the test code size. The method consists of three parametric phases and can deal with different VLIW processor models. The main goal of the proposed method is to automatically obtain a test program able to effectively reduce the test time and the required resources. Experimental results gathered on a case study show the effectiveness of the proposed approach.

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Abstract: While the shrinking of minimum dimensions of integrated circuits till tenths of nanometers allows the integration of millions of gates on the single chip, it also implies the growth of the importance of effects that could reduce the reliability of circuits. In particular, the reduced integration step, the reduced supply voltage that lowers the noise immunity, the growing power needs, the eventual integration of both digital and analog circuits on the same chip and the highly growing of radiation sensitivity [1], [2], [3] require an accurate evaluation of possible reliability reduction for the occurrence of: • permanent faults due to the aging of device materials [4], the interruptions of metal interconnections due to electromigration [5] or the crack of the insulation oxide of transistor [6]; • transient faults, known as Single Event Effects (SEE), which are much more likely than in the past due to the reduced transistors' sizes [3]: in particular new technology devices are more prone to crosstalk in the interconnects and to radiation effects.

A New Fault Injection Approach for Testing Network-on-Chips

Abstract: Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively replacing global on-chip interconnections in Multi-processor System-on-Chips (MP-SoCs) thanks to better performances and lower power consumption However, modern generations of MP-SoCs have an increasing sensitivity to faults due to the progressive shrinking technology Consequently, in order to evaluate the fault sensitivity in NoC architectures, there is the need of accurate test solution which allows to evaluate the fault tolerance capability of NoCs This paper presents an innovative test architecture based on a dual-processor system which is able to extensively test mesh based NoCs The proposed solution improves previously developed methods since it is based on a NoC physical implementation which allows to investigate the effects induced by several kind of faults thanks to the execution of on-line fault injection within all the network interface and router resources during NoC run-time operations The solution has been physically implemented on an FPGA platform using a NoC emulation model adopting standard communication protocols The obtained results demonstrated the effectiveness of the developed solution in term of testability and diagnostic capabilities and make our solutions suitable for testing large scale NoC design

Latch-up test measurement for long duration space missions

Abstract: Long duration space missions require extremely high reliable components that must guarantee components functionality without incurring in damaging effects. When Integrated Circuits (ICs) are considered, radiation hardened technology should be mandatorily adopted, since it allows to adequately protect against Single Event Latchup (SEL). In this paper we present a complete test measurement experimental setup in order to measure the SEL occurrences at high temperature conditions. The SEL test setup and the executed experiments are described. The experimental environment has been used to test SEL effects in Gate Arrays MG2 Radiation Hardened technology with respect to strike of heavy ions. We performed a complete radiation test at GANIL radiation facility, executed at high temperature by monitoring current absorption and analyzing the functionality of the MSDRX ASIC core. Experimental results show that a drastic improvement of the device SEL sensitivity is observed for high power supply voltages.

FPGA-based serial links for SuperB: Design Issues Vs. Radiation Tolerance

Abstract: SuperB is a novel, high-luminosity (1036cm-2s-1), asymmetric e+e- collider to be built at the future Cabibbo Laboratory, in the campus of the University of Rome Tor Vergata (Italy). A detector aimed at studying the B physics will be installed in this facility. High-speed serial links will be used for trigger, control and data read-out. The on-detector ends of the links will have to withstand a hadron fluence of 8·1010cm-2 per effective year (107 s). In this work, we focus on the multi-gigabit bidirectional serial link architecture, which we implemented by means of GTP SerDes embedded in Xilinx Virtex-5 FPGA. We also performed proton irradiation tests of our designs and, with reference to the collected results, we discuss the effectiveness of the radiation mitigation techniques we employed.

On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors

Abstract: Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this chapter we present a new method that, starting from previously known algorithms, automatically generates an effective test program able to still reach high fault coverage on the VLIW processor under test, while minimizing the test duration and the test code size. Moreover, using this method, a set of small SBST programs can be generated aimed at the diagnosis of the VLIW processor. Experimental results gathered on a case study show the effectiveness of the proposed approach.

SEU effects on power consumption in FPGAs

Abstract: SEU effects in the configuration memory are the major cause of fault in SRAM-based FPGAs exposed to ionizing radiation. The mechanism of random changes in the device resource networks has been thoughtfully studied for their impact on the overall logic reliability and fault analysis, but much less effort has been paid in evaluating the effects on power consumption. In this paper, we present a detailed analysis of the quiescent consumption of a Xilinx Virtex 5 LX50T on the CORE, AUX, MGT and IO power domains during irradiation with 62-MeV proton beams. The tests have been performed at the Superconductive Cyclotron of the LNS-INFN facility (Catania, Italy). Changes in power consumption (most notably in the logic core) are experienced and these effects have to be taken into account when sizing the supply system, especially in applications with severe power budget issues like avionic equipment, satellite payloads and on-detector electronics in High Energy Physics Experiments. We also executed fault injection tests modifying programmable routing resources, in order to confirm or exclude possible fault mechanisms for the SEU-induced current variations.