Showing papers by "Luca Sterpone published in 2015"

Using Benchmarks for Radiation Testing of Microprocessors and FPGAs

Abstract: Performance benchmarks have been used over the years to compare different systems. These benchmarks can be useful for researchers trying to determine how changes to the technology, architecture, or compiler affect the system's performance. No such standard exists for systems deployed into high radiation environments, making it difficult to assess whether changes in the fabrication process, circuitry, architecture, or software affect reliability or radiation sensitivity. In this paper, we propose a benchmark suite for high-reliability systems that is designed for field-programmable gate arrays and microprocessors. We describe the development process and report neutron test data for the hardware and software benchmarks.

Layout and Radiation Tolerance Issues in High-Speed Links

Abstract: High-speed optical links are often used in trigger and data acquisition systems of High Energy Physics (HEP) experiments for data transfer, trigger and fast control distribution. Many experiments prefer the use of commercial off-the-shelf components (COTS) if possible, in order to avoid the non-recurrent engineering (NRE) costs and risks associated with the design of application specific integrated circuits. For the mentioned reason, static random access memory-based field programmable gate arrays (SRAM-based FPGAs) are usually deployed. However they are mostly used off-detector, where little or no radiation is present, since single event upsets in the configuration memory may alter the design functionality. In order to benefit from SRAM-based FPGAs also in radiation environments expected on-detector, suitable soft-error mitigation strategies must be adopted. In this work we evaluate the design trade-offs between performance and radiation-tolerance in a high-speed fixed-latency link based on a Virtex-5 SRAM-based FPGA. We evaluate different radiation mitigation strategies. Moreover, we experimentally verify some custom-developed placement and routing rules aimed at improving the FPGA firmware robustness against configuration upsets.

Analysis and mitigation of SEUs in ARM-based SoC on Xilinx Virtex-V SRAM-based FPGAs

Abstract: Technology scaling enables the Field Programmable Gate Arrays (FPGAs) provide increasing computing power while remain low power consumption. Together with the high flexibility for application design and deployment, FPGAs have become popular even in safety- and mission-critical applications. Meanwhile, Commercial Off-The-Shelf (COTS) components are often used in system design to reduce time-to-market and development cost. In this paper, we are proposing a new method for the analysis and mitigation of Single Event Upsets (SEUs) on SRAM-based FPGAs. The method is based on an analytical analyzer algorithm able to accurately estimate the application error rate; furthermore, the same developed algorithm is able to implement mitigation rules. We present the radiation experiment results for analysis and mitigation of Single Event Upsets (SEUs) in an ARM-based SoC implemented on Xilinx Virtex-V FPGA demonstrating the feasibility of the analysis tool and the effectiveness of the mitigation method.

On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAs

Abstract: Radiation-induced Soft Errors are widely known since the advent of dynamic RAM chips. Reconfigurable FPGA devices based on SRAM configuration memories are extremely sensitive to these effects resulting in an unwelcome change of behavior in digital logic. Indeed, soft errors occur today as a result of radiation from space or even at sea level. Detection, protection and mitigation of soft errors beyond aerospace and defence applications have been widely debated over the last decades. In the present paper we provide a complete design flow illustrating the proper design rules ranging from the synthesis, mapping and physical place and route algorithm tailored to the implementation of high performance and reliable SoCs using dynamic-reconfiguration oriented SRAM-based FPGAs. Radiation experimental results obtained radiation test performed using proton particles demonstrated the goodness of our developed design flow resulting in an overall error cross-section reduction of more than 2 orders of magnitude.

SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs

Abstract: Flash-based Field Programmable Gate Arrays (Flash-based FPGAs) are becoming more and more interesting for safety critical applications due to their re-programmability features while being non-volatile. However, Single Event Transients (SETs) in combinational logic represent their primary source of critical errors since they can propagate and change their shape traversing combinational paths and being broadened and amplified before sampled by sequential Flip-Flops. In this paper the SET sensitivity of circuits implemented in Flash-based FPGAs is mitigated with respect to the working frequency and different FPGA routing architecture. We outline a parametric routing scheme and placement and routing tools based on an iterative partitioning algorithm able to generate high performance circuits by reducing the wires delay and reducing the SET sensitivity. The efficiency of the proposed tools has been evaluated on a Microsemi Flash-based FPGA implementing different benchmark circuits including a RISC microprocessor. Experimental results demonstrated the reduction of SET sensitivity of more than 30% on the average versus state-of-the-art mitigation solutions and a performance improvement of about 10% of the nominal working frequency.