Showing papers by "Luca Sterpone published in 2017"

An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems

Abstract: Reconfigurable systems are gaining an increasing interest in the domain of safety-critical applications, for example in the space and avionic domains. In fact, the capability of reconfiguring the system during run-time execution and the high computational power of modern Field Programmable Gate Arrays (FPGAs) make these devices suitable for intensive data processing tasks. Moreover, such systems must also guarantee the abilities of self-awareness, self-diagnosis and self-repair in order to cope with errors due to the harsh conditions typically existing in some environments. In this paper we propose a self-repairing method for partially and dynamically reconfigurable systems applied at a fine-grain granularity level. Our method is able to detect correct and recover errors using the run-time capabilities offered by modern SRAM-based FPGAs. Fault injection campaigns have been executed on a dynamically reconfigurable system embedding a number of benchmark circuits. Experimental results demonstrate that our method achieves full detection of single and multiple errors, while significantly improving the system availability with respect to traditional error detection and correction methods.

Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs

Abstract: SRAM-Based FPGAs represent a low-cost alternative to ASIC device thanks to their high performance and design flexibility. In particular, for aerospace and avionics application fields, SRAM-based FPGAs are increasingly adopted for their configurability features making them a viable solution for long-time applications. However, these fields are characterized by a radiation environment that makes the technology extremely sensitive to radiation-induced Single Event Upsets (SEUs) in the SRAM-based FPGA's configuration memory. Configuration scrubbing and Triple Modular Redundancy (TMR) have been widely adopted in order to cope with SEU effects. However, modern FPGA devices are characterized by a heterogeneous routing resource distribution and a complex configuration memory mapping causing an increasing sensitivity to Cross Domain Errors affecting the TMR structure. In this paper we developed a new methodology to calculate the reliability of TMR architecture considering the intrinsic characteristics of the new generation of SRAM-based FPGAs. The method includes the analysis of the configuration bit sharing phenomena and of the routing long lines. We experimentally evaluate the method of various benchmark circuits evaluating the Mean Upset To Failure (MUTF). Finally, we used the results of the developed method to implement an improved design achieving 29x improvement of the MUTF.

Self rerouting of dynamically reconfigurable SRAM-based FPGAs

Abstract: Reconfigurable devices are widely attractive for several application fields thanks to their size, rapid prototyping characteristics, flexibility and upgradability. Thanks to partial Reconfiguration features, FPGA becomes the golden core of the adaptive computation paradigm since they may dynamically change their functionalities based on the elaboration request. Today, adaptive computation is mainly controlled at a coarse-grain granularity while no solutions exist to act at the fine granularity level especially to reprogram the FPGA routing interconnection. The purpose of this work is to propose an embedded core able to reconfigure the routing resources without the usage of external computational units. The developed core implements a Path Finding-based algorithm able to perform the full routability of complex designs. The core has been devised minimizing the area overhead and the requested computational power by wisely selecting a suitable subset of wiring segments. The functionalities of the core have been tested on a Xilinx SRAM-based FPGAs Zynq device using three different circuit benchmarks. Experimental results demonstrated that the core is able to successfully re-route almost 95% of the selected nets without introducing a relevant delay or area overhead.

Online monitoring soft errors in reconfigurable FPGA during radiation test

Abstract: Due to rapid technology scaling, electronic devices are becoming more susceptible against soft errors induced by radiation particles, which is a serious challenge for aerospace applications. Meanwhile Field Programmable Gate Array (FPGA) devices have been attracting attention in safety- and mission-critical applications in recent years with the increasing performance and flexibility they provide. Among different types of FPGAs according to the device technology, the SRAM-based FPGA has a higher sensitivity against soft errors as SRAM cell, which is used for storing the configuration data of the circuit design implemented and mapped on the FPGA, is one of the most sensitive devices against radiation induced soft errors. Hence, to guarantee the usage of SRAM-based FPGAs in safety critical environments, the design mapped on it requires an effective verification and validation procedure. Radiation test is one of the verification methods regarding the effects of radiation induced soft errors. In this paper, we present an automated setup for monitoring the soft errors during the radiation test and we compared the measurement obtained from radiation test with the one provided by analytical tools. The experimental results we gained demonstrated the feasibility of the proposed measurement platform.

Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach

Abstract: Ultra-scale devices based on technologies below 20nm are nowadays widely adopted due to their elevated computing features and low power consumption. These characteristics made them attractive even for fields where the high reliability is the major concern like automotive or aerospace ones. In order to guarantee a high reliability level, one of the major challenge in these application fields is the protection versus the micro latch-up effect: a phenomenon that temporarily affects the logical behavior of technology cells at various locations across the die provoking circuit misbehavior. In this paper, we propose a new analysis flow for detecting the occurrences of micro latch-up event considering the physical layout of a circuit. In details, a circuit layers has been developed in order to identify the micro latch-up sensitive points in the 3D layout geometry, while a Monte-Carlo approach has been developed to calculate the micro latch-up error rate on routing interconnection nodes. Experimental results have been performed by fault simulation on a benchmark circuit implemented in six different variants of routing congestions using a 15 nm COTS technology library demonstrating the feasibility of the proposed approach.

Radiation-induced SET on Flash-based FPGAs: Analysis and Filtering methods

Abstract: Reliability of Integrated Circuits (ICs) it is nowadays a major concern for deep sub-micron technology. The progressive decreasing of device feature sizes provokes an increasing sensitiveness to radiation-induced particle strikes within the device silicon structure generating a larger number of Single Event Transients (SETs). In the present paper, we propose a new analysis to characterize the SET phenomena within Flashbased FPGAs. Besides, we developed a new mitigation strategy based on the modification of the place and routed design to improve the filtering capability selectively adding electrical resistive capacitive loads without introducing performance degradation and introducing a limited overhead in terms of routing segments. Experimental results performed on a various set of benchmark circuits shows a mitigation of SET improved of 3 orders of magnitude with respect to traditional logical filtering solutions with a minimal performance degradation of about 9%.

Reliability evaluation of heterogeneous systems-on-chip for automotive ECUs

Abstract: Automotive systems embed an increasing number of heterogeneous devices and architectures that lead the effective reliability analysis a major challenge. With the advent of integrated Virtual Environment, complex system design and simulation have been made possible thanks to the integration of various simulator engines within a unique development platform. In this paper we develop a Fault Injection tool able to inject Single Event Upsets (SEUs) using a Virtual Prototype simulation environment. The developed method results powerful and effective to observe the overall system dependability and characterize the fault tolerance capability of any type of SW/HW module included in the system. Experimental results obtained with an analysis of a gear-shift automotive application demonstrated the feasibility of the developed method.

Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs

Abstract: Due to the decreasing feature sizes of VLSI circuits, radiation induced Single Event Transients (SETs) are increasingly dominating the event ratio on modern VLSI devices In particular, Flash-based FPGAs are characterized by the main concern of radiation-induced voltage glitches or SETs in the combinational logic Transient pulses can be sampled by a storage element and can propagate through the circuit up to the outputs and leading to an error In this paper, we propose a complete implementation flow including sensitivity analysis, fault tolerant mapping and fault tolerance-oriented place and route for the effective design of SET tolerant circuits on Flash-based FPGAs In details, the proposed method allows accurate measurement of the transient pulse source induced by radiation particles and estimation of the SET error rate on the overall circuit Besides the developed method provides a netlist mapping and place and route tool for the selective mitigation of SET effects The proposed method has been applied to an industrial design oriented to the Euclid European Space Agency mission including more than ten different modules The obtained results show an improvement of the total filtering capability of around 43 times with respect to the original netlist without affecting the timing constraints of the circuit

Fault tolerant electronic system design

Abstract: Due to technology scaling, which means smaller transistor, lower voltage and more aggressive clock frequency, VLSI devices are becoming more susceptible against soft errors. Especially for those devices deployed in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena (e.g. aging and wear-out effects) also have negative impacts on reliability of modern circuits. Furthermore, as recent researches show that even at sea level, radiation particles can still induce soft errors in electronic systems, for avionic and space applications, certain fault tolerant strategy must be applied to guarantee system reliability throughout application lifetime. In this paper, we focus on two aspects: testing for System-on-Chip/System-on-Programmable-Chip by exploiting debug infrastructures and analysis and mitigation of Single Event Effects on FPGA devices.

Effective Characterization of Radiation-induced SET on Flash-based FPGAs

Abstract: Single Event Transients (SETs) are one of the major concern for Flash-based Field Programmable Gate Arrays (FPGAs). In this paper, we propose a new analysis to characterize the SET phenomena within Flash-based FPGAs.