Showing papers by "Luca Sterpone published in 2018"

PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing

Abstract: In the last decades, FPGAs have been increasingly used in many different mission critical applications, such as the avionics and aerospace ones. Thus, research interest in studying faults in FPGAs has seen a sharp increase, especially for those applications that require high dependability and must operate in harsh environments. The increase of resources available in FPGA devices has caused a huge growth in routing complexity. Nowadays, more than 80% of transistors in modern FPGAs are related to the routing infrastructure. The analysis of faults related to routing structure of FPGA devices is a hard task due to the lack of tools working at low-level, limited information availability about interconnection structure from vendors and, above all, no automated testing workflow for such kind of resources. In this paper, we introduce PyXEL, an integrated environment realized to automatize the analysis of fault effects in FPGAs routing structure. PyXEL is a Python-based framework that allows to easily manipulate FPGAs bitstreams in order to inject specific faults and to analyze their behavior. Moreover, PyXEL provides an easy way to build and run experimental workflow interacting directly with Xilinx Vivado and ISE allowing to select routing resources to test and logically analyze results. We demonstrated the feasibility and the advantages of our approach exploiting PyXEL to gain insight into the electrical effects of faults in the routing interconnections of the Xilinx Artix-7.

About the functional test of the GPGPU scheduler

Abstract: General Purpose Graphical Processing Units (GPGPUs) are increasingly used in safety critical applications such as the automotive ones. Hence, techniques are required to test them during the operational phase with respect to possible permanent faults arising when the device is already deployed in the field. Functional tests adopting Software-based Self-test (SBST) are an effective solution since they provide benefits in terms of intrusiveness, flexibility and test duration. While the development of the functional test code addressing the several computational cores composing a GPGPU can be done resorting to known methods developed for CPUs, for other modules which are typical of a GPGPU we still miss effective solutions. This paper focuses on one of the most relevant module consists on the scheduler core which is in charge of managing different scalar computational cores and the different executed threads. At first, we propose a method for evaluating the fault coverage that can be achieved using an application program. Then, we provide some guidelines for improving the achieved fault coverage. Experimental results are provided on an open-source VHDL model of a GPGPU.

COMET: a Configuration Memory Tool to Analyze, Visualize and Manipulate FPGAs Bitstream

Abstract: Nowadays Xilinx Tools trend is to increase design abstraction level. This allows users to create complex FPGA-based projects and designs without the needs of in-depth knowledge of low level resources implementation and configuration memory usage. The design automation has the advantage to make the development process more rapid and affordable for a larger range of users. On the other hand, this trend has the drawback of the lack of accessibility to low level information, above all on FPGA fabric and configuration memory. This is crucial in research, especially the one oriented to the development of specific mission critical applications. In the aerospace fields an in-depth knowledge of the device is fundamental to guarantee high performances and high dependability to the application. In this paper we propose COMET: an interface at the lowest level to enable the study of SRAM-based FPGA's configuration memory, allowing the visualization, the analysis and the manipulation of its content. This tool allows bitstream decryption and, bitstream fine-grained modification as consequence. These features provide efficient means to perform detailed fault injection and simulation or to cleverly perform Partial Dynamic Reconfiguration, increasing dependability and performances of FPGA-based aerospace mission critical applications.

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs

Abstract: SRAM-based FPGA devices manufactured in FinFET technologies provide performances and characteristics suitable for avionics andaerospace applications. The estimation of error rate sensitivity to harsh environments is a major concern for enabling their usage on such application fields. In this paper, we propose a new estimation approach able to consider the radiation effects on the configuration memory and logic layer of FPGAs, providing a comprehensive Application Error Rate probability estimation. Experimental results provide a comparison between radiation test campaigns, which demonstrates the feasibility of the proposed solution.

Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach

Abstract: Reconfigurable SRAM-based FPGAs are increasingly attractive for high performance reconfigurable computing cores due to their flexibility, upgradability and computational capabilities. In general, Partial Reconfiguration (PR) improves the reconfigurable computing paradigm due to the possibility to modify only a portion of the FPGA’s configuration memory, which results in reduced reconfiguration time. However, the speed-up gain SRAM-based FPGAs are able to achieve relies on the efficiency of the mechanism adopted to load frames in the FPGA’s configuration memory. Despite the advantages of configuration memory Partial Reconfiguration, the lack of tools and design software to implement efficient frame-oriented configuration makes PR performance less powerful then expectation. In this work, we propose an approach to reduce the reconfiguration time of routing resources exploiting a frame-driven routing algorithm able to drastically reduce the number of configuration memory frames used in the design. The advantage of the proposed solution has been applied to several benchmark circuits implemented with our routing algorithm on a Xilinx Kintex-7 SRAM-based FPGA. Experimental results shown a reduction of the used configuration frames of more than 40% on the average and a measured reconfiguration time reduced of more than 35% with respect to traditional reconfiguration approaches.

MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories

Abstract: Modern Field Programmable Gate Arrays (FPGAs) embed dedicated blocks for Memories (BRAMs), digital signal processing (DSPs) and hardwired microprocessors merged with the reconfigurable logic array. This trend, coupled with Error Correction Code (ECC) mechanism and Dynamic Partial Reconfiguration (DPR), makes these devices ideal candidates for mission critical applications where high reliability is a strict requirement. Therefore, efficient and in-field testing became a major concern. Unfortunately, typical on-line memory testing approaches are not fully optimized for the reconfigurable scenario. In fact, a suitable fault model should be considered in order to enhance the fault coverage and reduce the test redundancy. In this work, we proposed the MATS** algorithm, which is able to reduce the execution time and optimize the fault coverage with respect to most popular embedded memories March Tests. Furthermore, MATS** results to be highly suitable to be executed, even partially, in brief time slots available within the device mission. Experimental results show that our approach is around 30% faster than state-of-the-art solutions while achieving the optimal fault coverage.

OLT(RE) 2 : An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems

Abstract: Reconfigurable systems gained great interest in a wide range of application fields, including aerospace, where electronic devices are exposed to a very harsh working environment. Commercial SRAM-based FPGA devices represent an extremely interesting hardware platform for this kind of systems since they combine low cost with the possibility to utilize state-of-the-art processing power as well as the flexibility of reconfigurable hardware. In this paper we present OLT(RE) $^2$ : an on-line on-demand approach to test permanent faults induced by radiation in reconfigurable systems used in space missions. The proposed approach relies on a test circuit and on custom place and route algorithms. OLT(RE) $^2$ exploits partial dynamic reconfigurability offered by today's SRAM-based FPGAs to place the test circuits at run-time. The goal of OLT(RE) $^2$ is to test unprogrammed areas of the FPGA before using them, thus preventing functional modules of the reconfigurable system to be placed on areas with faulty resources. Experimental results have shown that (i) it is possible to generate, place and route the test circuits needed to detect on average more than 99 percent of the physical wires and on average about 97 percent of the programmable interconnection points of an arbitrary large region of the FPGA in a reasonable time and that (ii) it is possible to download and run the whole test suite on the target device without interfering with the normal functioning of the system.

A Zero-Timing Overhead SET Mitigation Approach for Flash-based FPGAs

Abstract: Reliability of Integrated Circuits (ICs) is nowadays a major concern for sub-micron technologies especially when they are adopted in mission critical applications. The decreasing of device feature size leads to an increasing of the device sensitivity against Single Event Effects (SEEs), especially Single Event Transients (SETs), induced particle strikes within the device silicon structure. Flash-based FPGA is a golden core for aerospace safety critical applications; however, traditional SET mitigation solutions, such as filter insertion, can lead to performance degradation of the implemented design. In this paper, we provide a new implementation flow that is able to evaluate the SET phenomena considering its specific convergence case and effectively mitigate the SETs without introducing any performance penalization to the original netlist. Experimental results on different sets of benchmark circuits demonstrated the mitigation of SET events without affecting the timing performances of the circuits.

On the mitigation of single event transients on flash-based FPGAs

Abstract: Thanks to the immunity against Single Event Upsets in configuration memory, Flash-based FPGA is becoming widely adopted in mission- and safety-critical applications, such as in aerospace field. However, the decreasing of device feature size leads to an increasing of the device sensitivity regarding Single Event Transients (SETs). In this paper, we developed a new workflow to evaluate SET phenomena in a specific convergence case and introduce a new mitigation of SET pulse without introducing any performance penalization to the original netlist.

SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs

Abstract: Flash-based Field Programmable Gate Array (FPGA) devices are nowadays golden cores of many applications especially in space and avionic fields where reliability is becoming an important concern. In particular, for Flash-based FPGAs when adopted in those applications, the main concern is radiation-induced voltage glitched know as Single Event Transient (SET) in the combinational logic. In this work, a new CAD tool has been developed in order to evaluate the sensitivity of the implemented circuit regarding SET and to mitigate their effects. The proposed tool has been applied to an industrial design adopted by the EUCLID space mission including more than ten different modules. The experimental results demonstrated the feasibility and efficiency of proposed tool.

IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs

Abstract: Nowadays SRAM-based FPGAs, already widely used for their advantages in terms of size, flexibility and performances, are becoming even more attractive since they may dynamically change their functionalities based on the elaboration demand, thanks to Dynamic Partial Reconfiguration Feature. In these systems the communication infrastructure represents the major performance bottleneck due to routing congestions and to the needs to guarantee signal integrity at the module boundaries. In this paper we propose an Interface-based communication architecture, which simplify the interaction mechanism and the DRPM architecture, reducing both delay and resources overhead with respect to the state-of-the-art solutions.