Showing papers by "Luca Sterpone published in 2021"

SEU Evaluation of Hardened-by-Replication Software in RISC- V Soft Processor

Abstract: The interest of the space industry around soft processors is increasing. However, the advantages in terms of costs and customizability provided by soft processors are countered by the reliability issues deriving by Single Event Effects, especially Single Event Upsets. Several techniques have been proposed to tackle these issues, both at the hardware- and software levels. Software approaches rely on replicating data and computations to cope with SEUs affecting the memory where the binary code is stored. Thanks to open licenses, RISC-V solutions are steadily growing in popularity among the set of available soft processors. In this works, we present a reliability evaluation of four different benchmarks running on the RI5CY soft processor implemented on SRAM-based FPGAs. The reliability of the baseline and hardened-by-replication versions of the software benchmarks are evaluated against SEUs-induced faults both at the software and hardware architecture levels through fault injection campaigns in the microprocessor memory and configuration memory, respectively. Results assess how the adoption of the hardening-by-replication technique at the software level slightly improves reliability against software-related faults but degrades reliability against architectural faults, making it an inefficient solution when it is not combined with hardware robustness.

A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication

Abstract: Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology. The proposed design is hardened against transient errors by selective duplication of sensitive transistors based on a comprehensive radiation-sensitivity analysis. Experimental results show a 62% reduction in the SET sensitivity of the proposed design with respect to the unhardened one. Moreover, the proposed hardening technique leads to improvement in performance and power overhead and zero area overhead with respect to the state-of-the-art techniques applied to the unhardened full-adder cell.

A New Domains-based Isolation Design Flow for Reconfigurable SoCs

Abstract: Reconfigurable SoCs are widely adopted in mission-critical tasks in aerospace and automotive. Though, one of their main drawbacks is the susceptibility to high-energy particles both in space and at sea level. Isolation Design Flow is a promising implementation approach to improve the reliability of circuits. However, considering the high number of modules in a complex circuit, especially when redundant techniques are applied, IDF requires a complex floorplanning stage. In this paper, the benefits of using IDF are evaluated, both for plain and hardened-by-redundancy designs. We propose an implementation methodology to tackle the complexity of applying IDF to TMR-based circuits that usually make the implementation approach unfeasible. The impact of different design policies on the reliability of the system is evaluated through fault injection campaigns. The proposed method is applied to the TMR-hardened CORDIC core implemented on Zynq AP-SoC and compared with other possible solutions. The results report a significant improvement in the TMR effectiveness when the proposed domains-based IDF is applied.

DYRE: a DYnamic REconfigurable solution to increase GPGPU’s reliability

Abstract: General-purpose graphics processing units (GPGPUs) are extensively used in high-performance computing. However, it is well known that these devices’ reliability may be limited by the rising of faults at the hardware level. This work introduces a flexible solution to detect and mitigate permanent faults affecting the execution units in these parallel devices. The proposed solution is based on adding some spare modules to perform two in-field operations: detecting and mitigating faults. The solution takes advantage of the regularity of the execution units in the device to avoid significant design changes and reduce the overhead. The proposed solution was evaluated in terms of reliability improvement and area, performance, and power overhead costs. For this purpose, we resorted to a micro-architectural open-source GPGPU model (FlexGripPlus). Experimental results show that the proposed solution can extend the reliability by up to 57%, with overhead costs lower than 2% and 8% in area and power, respectively.

On the Evaluation of SEEs on Open-Source Embedded Static RAMs

Abstract: Static RAM modules are widely adopted in high performance systems. Single Event Effects (SEEs) resilient memories are required in many embedded systems applied in automotive and aerospace applications to increase their overall resiliency against SEEs. The current SEE resilient SRAM modules are obtained by applying radiation-hardened by design solutions which leads to elevated area overhead and difficulty to tune the resiliency capability with respect to the particle's radiation profile. To overcome these limitations, we propose a methodology for the analysis and mitigation of embedded SRAMs generated by the OpenRAM memory compiler. A technology-oriented radiation analysis tool is presented to support the interaction of the charged radiation particles with the SRAM layout and depict the sensitive transistors of the SRAM memory. A selective duplication of the sensitive transistors has been applied to the 6T-SRAM cell designed at the layout level. The designed cell is included in the OpenRAM compiler and used to generate a mitigated 8Kb SRAM-bank. We evaluated the SEEs sensitivity by comparative simulation-based radiation analysis observing a reduction more than 6 times with respect to the original 6T-SRAM cell for the SEE sensitivity at high energy heavy ions particles, with negligible degradation of operations margins and power consumption and area overhead of less than $\sim$ 4%.

A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor

Abstract: Three-dimensional Integrated Circuits (3-D ICs) have gained much attention as a promising approach to increase IC performance due to their several advantages in terms of integration density, power dissipation, and achievable clock frequencies. However, achieving a 3-D ICs resilient to soft errors resulting from radiation effects is a challenging problem. Traditional Radiation-Hardened-by-Design (RHBD) techniques are costly in terms of area, power, and performance overheads. In this work, we propose a new 3-D LUT design integrating error detection capabilities. The LUT has been designed on a two tiers IC model improving radiation resiliency by selective upsizing of sensitive transistors. Besides, an in-silicon radiation sensor adopting inverters chain has been implemented within the free volume of the 3-D structure. The proposed design shows a 37% reduction in sensitivity to SETs and an effective error detection rate of 83% without introducing any area overhead.

A Neutron Generator Testing Platform for the Radiation Analysis of SRAM-based FPGAs

Abstract: SRAM-based Field Programmable Gate Arrays (FPGAs) represent an attractive solution for mission-critical computationally intensive applications due to their high integration, flexibility, and computational capabilities. However, the static memory cells of SRAM-based configuration memory present a high sensitivity to radiation effects. Due to the increasing interest in using these devices in radiation environments such as aerospace and high energy physics, the evaluation of their reliability through radiation tests is a key role in their validation. Radiation Testing consists in exposing the physical device to radioactive source or radiation beams and represents an accurate solution for evaluating the device sensitivity. However, this implies high costs both in terms of experimental setup and money due to the low availability of the required facilities. Among the possible solutions, neutron generator testing would represent an efficient solution even if challenging from the instrumentation needed for the experimental setup. In this work, we present a test instrumentation and methodology specific for cost-effective short-time neutron generator testing to efficiently evaluate FPGA radiation-induced soft error sensitivity.