Luca Sterpone

TL;DR: It was demonstrated that MVs contained ribonucleoproteins involved in the intracellular traffic of RNA and selected pattern of miRNAs, suggesting a dynamic regulation of RNA compartmentalization in MVs.

TL;DR: The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 4.03% to 0.98% the number of upsets in the routing able to cause an error in theTMR circuit.

TL;DR: A reliability-oriented place and route algorithm is presented that is able to effectively mitigate the effects of the considered faults and is demonstrated by extensive fault injection experiments showing that the capability of tolerating SEU effects in the FPGA's configuration memory increases up to 85 times with respect to a standard TMR design technique.

TL;DR: In this paper, the authors describe a system based on partial reconfiguration for running fault-injection experiments within the configuration memory of SRAM-based FPGAs, which uses the internal configuration capabilities that modern FPGA offer in order to inject SEU within configuration memory.

TL;DR: In this article, the authors present an analysis of the SEU effects in circuits hardened according to Triple Module Redundancy to investigate the possibilities of successfully applying TMR to designs mapped on commercial-off-the-shelf SRAM-based FPGAs, which are not radiation hardened.