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Luca Sterpone

Researcher at Polytechnic University of Turin

Publications -  236
Citations -  3523

Luca Sterpone is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault injection & Field-programmable gate array. The author has an hindex of 24, co-authored 222 publications receiving 3125 citations. Previous affiliations of Luca Sterpone include Instituto Politécnico Nacional.

Papers
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Journal ArticleDOI

Radiation-induced Single Event Transient effects during the reconfiguration process of SRAM-based FPGAs

TL;DR: An evaluation methodology for the errors caused by SETs during the reconfiguration of the configuration memory in SRAM-based FPGAs is presented and the obtained results are reported.
Proceedings ArticleDOI

Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features

TL;DR: A new methodology is presented which uses machine learning clustering techniques to group flip-flops with similar expected contributions to the overall functional failure rate, based on the analysis of a compact set of features combining attributes from static elements and dynamic elements.
Proceedings ArticleDOI

Fault injection analysis of transient faults in clustered VLIW processors

TL;DR: The cross-domain failures affecting redundant mitigation techniques implemented on a statistically scheduled data path VLIW processor are analyzed and a fault injection analysis of transient faults affecting the r-VEX V LIW processor implemented on an FPGA platform is described.
Proceedings ArticleDOI

A new solution to on-line detection of Control Flow Errors

TL;DR: This paper focuses on Control Flow Errors (CFEs) and extends a previously proposed method, based on the usage of the debug interface existing in several processors/controllers, that achieves a good detection capability with very limited impact on the system development flow and reduced hardware cost.
Proceedings ArticleDOI

An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques

TL;DR: System knowledge-based hardening techniques using recursive structures for the implementation of moving average filters that provide protection against single event upsets are evaluated through two fault injection systems based on simulation and emulation respectively.