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Luca Sterpone
Researcher at Polytechnic University of Turin
Publications - 236
Citations - 3523
Luca Sterpone is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault injection & Field-programmable gate array. The author has an hindex of 24, co-authored 222 publications receiving 3125 citations. Previous affiliations of Luca Sterpone include Instituto Politécnico Nacional.
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Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications
TL;DR: This research presents re-configurable Field Programmable Gate Arrays, a next generation of FPGAs that can be hardened with radiation hardened SRAM-based FPGA technology.
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New Techniques for Improving the Performance of the Lockstep Architecture for SEEs Mitigation in FPGA Embedded Processors
TL;DR: A non invasive approach for the implementation of fault tolerant systems based on COTS processors embedded in FPGAs, using lockstep in conjunction with checkpoint and rollback recovery, is presented.
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A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing
TL;DR: A new algorithm for the analysis of critical radiation effects, in particular, related to Single Event Upset (SEUs) and Multiple Event Upsets (MEUs) has been developed to obtain an effective estimation of the radiation impact and enabling the tuning of the component mapping reducing the routing interaction between the reconfigurable placed modules in their different feasible positions.
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FlexGripPlus: An improved GPGPU model to support reliability analysis
TL;DR: This work extended the capabilities of an open-source VHDL GPGPU model (FlexGrip) and developed a new version named FlexGripPlus to study and analyze the effects of SEUs in a GPG PU in a much more detailed manner, demonstrating the correlation between the number of execution units in aGPGPU and the system reliability.
Proceedings ArticleDOI
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
TL;DR: A reliability-oriented place and route algorithm able to significantly improve the reliability of SRAM-based FPGAs with limited costs in terms of performance degradation and resource occupation is devised.