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Luca Sterpone

Researcher at Polytechnic University of Turin

Publications -  236
Citations -  3523

Luca Sterpone is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault injection & Field-programmable gate array. The author has an hindex of 24, co-authored 222 publications receiving 3125 citations. Previous affiliations of Luca Sterpone include Instituto Politécnico Nacional.

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Book ChapterDOI

SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs

TL;DR: A parametric routing scheme and placement and routing tools based on an iterative partitioning algorithm able to generate high performance circuits by reducing the wires delay and reducing the SET sensitivity are outlined.
Journal ArticleDOI

A comparative radiation analysis of reconfigurable memory technologies: FinFET versus bulk CMOS

TL;DR: In this article , a comparative radiation reliability analysis between two reconfigurable devices with different manufacturing technology: 28 nm CMOS-based and 16 nm FinFET based FPGAs is presented.
Proceedings ArticleDOI

On the Evaluation of SEEs on Open-Source Embedded Static RAMs

TL;DR: In this paper, a methodology for the analysis and mitigation of embedded SRAMs generated by the OpenRAM memory compiler is proposed to support the interaction of the charged radiation particles with the SRAM layout and depict the sensitive transistors of SRAM memory.
Proceedings ArticleDOI

A new hardware architecture for performing the gridding of DNA microarray images

TL;DR: A novel hardware acceleration architecture specifically designed to process DNA microarray images is presented and shows a reduction of the computation time of one order of magnitude if compared with previously developed software-based approach.
Journal ArticleDOI

DYRE: a DYnamic REconfigurable solution to increase GPGPU’s reliability

TL;DR: This work introduces a flexible solution to detect and mitigate permanent faults affecting the execution units in these parallel devices, based on adding some spare modules to perform two in-field operations: detecting and mitigating faults.