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Author

Luu Nguyen

Bio: Luu Nguyen is an academic researcher from National Semiconductor. The author has contributed to research in topics: Flip chip & Chip-scale package. The author has an hindex of 9, co-authored 10 publications receiving 852 citations.

Papers
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Journal ArticleDOI
TL;DR: A review of fourteen solder joint fatigue models is presented in this article with an emphasis on summarizing the features and applications of each fatigue model, and two fatigue model application scenarios are discussed.

487 citations

Patent
08 Aug 2000
TL;DR: An imaging sensor module assembly adapted to be mounted to a substrate for use in electronic imaging devices is described in this paper, which includes an optical lens, and a sensor package having a sensor surface containing an optical detector portion.
Abstract: An imaging sensor module assembly adapted to be mounted to a substrate for use in electronic imaging devices. The imaging sensor includes an optical lens, and a sensor package having a sensor surface containing an optical detector portion. The sensor further includes a plurality of sensor contacts in electrical communication with the optical detector portion. A flex circuit includes a plurality of circuits terminating at respective terminals electrically coupled to a corresponding sensor contact. The module assembly further includes a lens housing assembly configured to support the optical lens, and a barrel portion adapted to fixedly couple to the sensor package. This coupling orients the lens a predetermined focal length from the sensor package such that light waves passing through the lens are focused onto the optical detector portion.

115 citations

Patent
22 Jul 1999
TL;DR: In this paper, a method and apparatus for forming a layer of underfill encapsulant on an integrated circuit located on a wafer is described, where the integrated circuit is mounted to a substrate and the substrate and integrated circuit are electrically coupled by a solder reflow operation.
Abstract: A method and apparatus for forming a layer of underfill encapsulant on an integrated circuit located on a wafer are described. As a flip chip, the integrated circuit has electrically conductive pads, most of which have a solder ball attached thereto. Most of the solder balls have been flattened in order to provide an enlarged solder wetting area. A layer of underfill encapsulant is injected onto the integrated circuit under pressure to form a layer of underfill encapsulant that is then pre-cured. The integrated circuit is mounted to a substrate and the substrate and the integrated circuit are electrically coupled by a solder reflow operation which also finally cures the underfill encapsulant.

90 citations

Patent
18 Jun 1999
TL;DR: In this paper, a method and an apparatus for forming a plastic chip on chip module is described, which is formed by placing a stacked chip set into a molding chamber suitably arranged to receive encapsulant.
Abstract: A method and an apparatus for forming a plastic chip on chip module is disclosed. The plastic chip on chip module is formed by placing a stacked chip set into a molding chamber suitably arranged to receive encapsulant. The stacked chip set includes a daughter chip that is electrically and mechanically coupled to a mother chip where the daughter chip is directly aligned to and separated from the mother chip by a standoff gap. Encapsulant is then passed into the molding chamber filling the standoff gap substantially simultaneously with surrounding the chip set to form the plastic chip on chip module.

87 citations

Proceedings ArticleDOI
21 May 2000
TL;DR: In this article, a joint venture program, sponsored by the Advanced Technology Program (ATP), was formed to explore the next paradigm shift in flip chip packaging technology, namely, processing underfill at the wafer level.
Abstract: In the last few years, flip chip technology has been increasingly employed in a variety of applications in the microelectronics industry. Comparing to conventional wirebonding technology, flip chip provides lower profile, faster signal transfer, and higher I/O density. One of the key materials used in flip chip is the underfill encapsulant, which enhances the reliability of the flip chip device by more than an order of magnitude. Currently, underfilling is carried out at the package level, e.g., each chip has to be processed individually after solder reflow. The encapsulant has to be post-cured subsequently off-line. The slow underfilling process becomes a bottleneck in the high volume manufacturing of flip chip. A joint venture program, sponsored by the Advanced Technology Program (ATP), was formed to explore the next paradigm shift in flip chip packaging technology, namely, processing underfill at the wafer level. In this process, the underfill is deposited on the wafer prior to dicing. At the assembly stage, the singulated die is processed as in standard flip chip reflow operations. The main difference is that the pre-coated underfill with built-in flux will cure concurrently with the reflow of the solder, allowing both electrical and structural interconnection to be achieved simultaneously. Therefore, this wafer level underfill process offers much potential in terms of reduced production time and increased throughput. The process will be directly suitable for high volume production using the existing assembly infrastructure, lowering the cost of implementation. In this paper, the technical challenges and the solutions for both materials development and process verification in this program will be discussed.

27 citations


Cited by
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Patent
21 Jul 1998
TL;DR: In this article, a flip-chip attachment of a chip (10) to a substrate (20) is provided by pre-coating the chip with an encapsulant underfill material (22) having discrete solder columns therein to eliminate the conventional capillary flow underfill process.
Abstract: A simplified process for flip-chip attachment of a chip (10) to a substrate (20) is provided by pre-coating the chip (10) with an encapsulant underfill material (22) having discrete solder columns therein to eliminate the conventional capillary flow underfill process. Such a structure permits incorporation of remeltable layers for rework, test, or repair. It also allows incorporation of electrical redistribution layers. In one aspect, the chip (10) and pre-coated encapsulant are placed at an angle to the substrate and brought into contact with the pre-coated substrate, then the chip (10) and pre-coated encapsulant are pivoted about the first point of contact, expelling any gas therebetween until the solder bumps (14) on the chip are fully in contact with the substrate (20). There is provided a flip-chip configuration having a compliant solder/flexible encapsulant understructure that deforms generally laterally with the substrate (20) as the substrate (20) undergoes expansion and contraction. With this configuration, the compliant solder/flexible encapsulant understructure absorbs the strain caused by the substrate without bending the chip (10) and substrate (20).

551 citations

Journal ArticleDOI
TL;DR: An overview of the major failure mechanisms of IGBT modules and their handling methods in power converter systems improving reliability is presented in this article, where fault-tolerant strategies for improving the reliability of power electronic systems under field operation are explained and compared in terms of performance and cost.
Abstract: Power electronics plays an important role in a wide range of applications in order to achieve high efficiency and performance. Increasing efforts are being made to improve the reliability of power electronics systems to ensure compliance with more stringent constraints on cost, safety, and availability in different applications. This paper presents an overview of the major failure mechanisms of IGBT modules and their handling methods in power converter systems improving reliability. The major failure mechanisms of IGBT modules are presented first, and methods for predicting lifetime and estimating the junction temperature of IGBT modules are then discussed. Subsequently, different methods for detecting open- and short-circuit faults are presented. Finally, fault-tolerant strategies for improving the reliability of power electronic systems under field operation are explained and compared in terms of performance and cost.

466 citations

Proceedings ArticleDOI
Ahmer Syed1
01 Jun 2004
TL;DR: In this paper, the authors describe in detail the life prediction models for SnAgCu solder joints, which are based on published constitutive equations for this alloy and thermal cycle fatigue data on actual components.
Abstract: Pb free solder is fast becoming a reality in electronic manufacturing due to marketing and legislative pressures. The industry has pretty much concluded that various versions of SnAgCu solder alloy offer the best alternative for eutectic Sn/Pb solder currently in use. With the current trend of cheaper, faster, and better electronic equipment, it has become increasingly important to evaluate the package and system performance very early in the design cycle using simulation tools. This requires life prediction models for new solder alloy systems so that the package-to-board interconnect reliability can be predicted for various environmental and field conditions. This paper describes in detail the life prediction models for SnAgCu solder joints. The models are based on published constitutive equations for this alloy and thermal cycle fatigue data on actual components. The approach uses advanced finite element modeling and analysis techniques and is based on mechanics of deformation. Both accumulated creep strain and creep strain energy density based models are developed. The model has been correlated with a number of data points and predicts life within 25% in most cases. The framework of modeling and prediction methodology described here is fully compatible with the framework used for SnPb solder previously.

353 citations

Journal ArticleDOI
TL;DR: In this paper, the authors present a method to estimate the inverter lifetime so that we can predict a failure prior to it actually happening, which can be used as a converter design tool or online lifetime estimation tool.
Abstract: This paper presents a method to estimate the inverter lifetime so that we can predict a failure prior to it actually happening. The key contribution of this study is to link the physics of the power devices to a large scale system simulation within a reasonable framework of time. By configuring this technique to a real system, it can be used as a converter design tool or online lifetime estimation tool. In this paper, the presented method is applied to the grid side inverter to show its validity. A power cycling test is designed to gather the lifetime data of a selected insulated gate bipolar transistor (IGBT) module (SKM50GB123D). Die-attach solder fatigue is found out to be the dominant failure mode of this IGBT module under the designed accelerated tests. Furthermore, the crack initiation is found to be highly stress dependent while the crack propagation is almost independent with stress level. Two different damage accumulation methods are used and the estimation results are compared.

326 citations

Patent
13 Mar 2006
TL;DR: In this paper, a method for making a semiconductor multi-package module, by providing a first package including a first substrate and having a die-up flip chip configuration, affixing a second package including another substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.
Abstract: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-up flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.

260 citations