M. Denais

TL;DR: In this article, the authors review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results, showing that the reliability of Hf-based materials is influenced both by the interfacial layer as well as the high k layer.

TL;DR: An overview of the evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented and a physical model is proposed which could be used to more accurately predict the transistor degradation.

TL;DR: An overview of evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented and a physical model is proposed which could be used to more accurately predict the transistor degradation.

TL;DR: In this article, the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide were investigated and a possible explanation for all configurations has been suggested.

TL;DR: In this article, the authors investigated recovery characteristics post NBTI stress when the recovery bias remains negative but lower in magnitude than the stress bias, consolidating the viewpoint involving role of hole trapping during NBTIs degradation, and showed that successive negative recovery biases can be applied to view trapping and detrapping behavior explicitly.