Author
M.F. Wang
Bio: M.F. Wang is an academic researcher. The author has an hindex of 1, co-authored 1 publications receiving 7 citations.
Papers
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25 Apr 2004
TL;DR: In this paper, the trap density at SiO/sub 2/Si interface, HfO/sensor/Sensor interface, and the bulk of stacked stacked HfOs/Sensors/SiO/Sub 2/sensors dielectrics are quantified with a simple charge pumping method.
Abstract: For the first time, trap density at SiO/sub 2//Si interface, HfO/sub 2//SiO/sub 2/ interface, and HfO/sub 2/ bulk of stacked HfO/sub 2//SiO/sub 2/ dielectrics are quantified respectively with a simple charge pumping method. It was found that the amount of each individual type of traps can be well correlated to specific process conditions as well as device performance, which makes such innovative characterization method very powerful for process optimization of high-k dielectrics.
7 citations
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TL;DR: In this article, the authors review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results, showing that the reliability of Hf-based materials is influenced both by the interfacial layer as well as the high k layer.
Abstract: High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.
499 citations
TL;DR: In this article, positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO 2/HfO2/TiN stacks.
Abstract: Positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO 2/HfO2/TiN stacks. Using gate stacks with varying thicknesses of the interfacial SiO2 layer (IL) or high-kappa layer and analysis for frequency-dependent CP data developed to address trap depth profiling, the authors have determined that the defect generation in the stress voltage range of practical importance occurs primarily within the IL on as-grown "precursor" defects most likely caused by the overlaying HfO2 layer. The generated traps can be passivated by a forming gas or nitrogen (N2 ) anneal, whereas a postanneal stress reactivates these defects. The results obtained identify the IL as one of the major targets for reliability improvement of high-kappa stacks
79 citations
TL;DR: In this article, a charge-pumping (CP) technique is proposed to simultaneously measure the border traps and interface-trap density (Dit) in high-kappa gate dielectric/Si interface.
Abstract: Charge-pumping (CP) technique is proposed to simultaneously measure the border traps and interface-trap density (Dit). The charge pumped per cycle (Qcp) versus high level (Vh ) of gate pulse for various frequencies was used to observe the behavior of the bulk traps close to the interface as a function of the CP frequency. Evolution on Qcp as a function of frequency was successfully used to determine the depth profile of border-trap density near the high-kappa gate dielectric/Si interface. The influence of border trap in high-kappa dielectric on the Dit measurement can be prevented by an appropriate selection of gate frequency in CP technique
22 citations
26 Mar 2006
TL;DR: In this paper, positive constant voltage stress combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO2/TiN stacks, and the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps was determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-κ gate stacks occurs primarily within the interfacial SiO 2 layer (IL) on the as-grown "precursor" defects most likely caused by the overlaying HfO2 layer.
Abstract: Positive constant voltage stress combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO2
19 citations
TL;DR: Various conventional and novel electrical characterization techniques have been combined with careful, robust analysis to properly evaluate high- κ gate dielectric stack structures to separate pre-existing defects that serve as fast transient charging and discharging sites from defects generated with stress.
16 citations