The author presents an algorithm which combines the pin assignment step and the global routing step in the physical design of VLSI circuits. The algorithm is based on two key theorems: the channel pin assignment theorem and the block boundary decomposition theorem. These two theorems deal successfully with the high complexity resulting from combining the pin assignment and global routing steps. According to these two theorems, one only needs to generate a coarse pin assignment and global routing solution. The exact pin locations and global routing topology can be determined optimally later by a linear time algorithm. The author implemented a pin assignment and global routine package named BeauticianGR based on the proposed algorithm. This package produces satisfactory results on test circuits. >

Pin assignment with global routing for general cell designs

New techniques are presented for routing L-shaped channels, switchboxes and staircases in 2-layer Manhattan-diagonal (MD) model with tracks in horizontal, vertical and /spl plusmn/45/spl deg/ directions. First, a simple O(l.d) time algorithm is proposed which routes any L-shaped channel with length l, density d and no cyclic vertical constraints, in w (d/spl les/w/spl les/d+1) tracks. Next, an O(l.w) time greedy method for routing an L-shaped channel with cyclic vertical constraints, is described. Then, the switchbox routing problem in the MD model is solved elegantly. These techniques, easily extendible to the routing of staircase channels, yield efficient solutions to detailed routing in general floorplans. Experimental results show significantly low via-count and reduced wire length, thus establishing the superiority of MD-routing over classical strategies.

Routing of L-shaped channels, switchboxes and staircases in Manhattan-diagonal model

Channel graphs for nonsliceable floorplans are studied for determination of feasible channel routing order. The minimum feedback vertex set (MFVS) formulation is revisited and a polynomial time heuristic is presented. It is shown that feasible routing orders with reserved channels, L-channels, and monotone channels can be obtained from a given MFVS for any floorplan. This approach provides a powerful tool to unify all three previous approaches and produces a solution with comparable efficiency and quality. >

The cycle structure of channel graphs in nonsliceable floorplans and a unified algorithm for feasible routing order

This paper presents an algorithm for identifying a maximal empty-staircase-polygon (MESP) of largest area, among a set of n points on a rectangular floor. A staircase polygon is an isothetic polygon bounded by two monotonically rising (falling) staircases. A monotonically rising staircase is a sequence of alternatingly horizontal and vertical line segments from the bottom-left corner of the floor to its top-right corner such that for every pair of points α = (xα, yα) and β = (xβ, yβ) on the staircase, xα ≤ xβ implies yα ≤ yβ. A monotonically falling staircase can similarly be defined from the bottom-right corner of the floor to its top-left corner. An empty staircase polygon is a MESP if it is not contained in another larger empty staircase polygon. The problem of recognizing the largest MESP is formulated using permutation graph, and a simple O(n3) time algorithm is proposed. Next, based on certain novel geometric properties of the problem, an improved algorithm is developed that identifies the largest MESP in O(n2) time and space. The algorithm can be easily tailored for identifying the widest MESP in a similar environment. The general problem of locating the largest area/width MESP among a set of isothetic polygonal obstacles, can be solved easily. These geometric optimization problems have several applications to VLSI layout design, robot motion planning, to name a few.

On finding an empty staircase polygon of largest area (width) in a planar point-set

A study is made of the problem of routing region definition and ordering in VLSI building-block layout design. An algorithm to decompose the routing area into straight channels and rectangular switchboxes corresponding to line segments in the routing structure of the placement such that the number of switchboxes is minimized, is presented. The algorithm is based on a graph-theory approach that makes use of an efficient polynomial time algorithm for computing minimum clique covers of triangulated graphs. Experimental results indicate that the algorithm performs well. For all the test problems considered, the algorithm consistently outperformed a previous known greedy algorithm, and it produced optimal solutions in all but one case. >

Channel/switchbox definition for VLSI building-block layout

A feasible channel-ordering algorithm for building-block layout using rectilinear blocks is presented. Existing approaches for layout with rectangular modules using only straight and L-shaped channels are no longer applicable. A class of channels called monotone channels is introduced. A monotone channel is a generalization of an L-shaped channel that has the form of a staircase. Routing is achieved by expanding the channel in both the horizontal and vertical directions. The algorithm produces a feasible channel order which minimizes the number of nonmonotone channels and the maximum number of corners in a channel used. >

M. Guruswamy

Papers

Channel routing order for building-block layout with rectilinear modules