M H Ben-Jamaa

Bio: M H Ben-Jamaa is an academic researcher from Commissariat à l'énergie atomique et aux énergies alternatives. The author has contributed to research in topics: Low-power electronics & AND-OR-Invert. The author has an hindex of 1, co-authored 1 publications receiving 83 citations.

An Efficient Gate Library for Ambipolar CNTFET Logic

Abstract: Recently, several emerging technologies have been reported as potential candidates for controllable ambipolar devices. Controllable ambipolarity is a desirable property that enables the on-line configurability of n-type and p-type device polarity. In this paper, we introduce a new design methodology for logic gates based on controllable ambipolar devices, with an emphasis on carbon nanotubes as the candidate technology. Our technique results in ambipolar gates with a higher expressive power than conventional complementary metal-oxidesemiconductor (CMOS) libraries. We propose a library of static ambipolar carbon nanotube field effect transistor (CNTFET) gates based on generalized NOR-NAND-AOI-OAI primitives, which efficiently implements XOR-based functions. Technology mapping of several multi-level logic benchmarks that extensively use the XOR function, including multipliers, adders, and linear circuits, with ambipolar CNTFET logic gates indicates that on average, it is possible to reduce the number of logic levels by 42%, the delay by 26%, and the power consumption by 32%, resulting in a energy-delay-product (EDP) reduction of 59 % over the same circuits mapped with unipolar CNTFET logic gates. Based on the projections in [1], where it is stated that defectfree CNTFETs will provide a 5x performance improvement over metal-oxide-semiconductor field effect transistors, the ambipolar library provides a performance improvement of 7x, a 57% reduction in power consumption, and a 20x improvement in EDP over the CMOS library.

Reconfigurable logic and neuromorphic circuits based on electrically tunable two-dimensional homojunctions

Abstract: Reconfigurable logic and neuromorphic devices are crucial for the development of high-performance computing. However, creating reconfigurable devices based on conventional complementary metal–oxide–semiconductor technology is challenging due to the limited field-effect characteristics of the fundamental silicon devices. Here we show that a homojunction device made from two-dimensional tungsten diselenide can exhibit diverse field-effect characteristics controlled by polarity combinations of the gate and drain voltage inputs. These electrically tunable devices can achieve reconfigurable multifunctional logic and neuromorphic capabilities. With the same logic circuit, we demonstrate a 2:1 multiplexer, D-latch and 1-bit full adder and subtractor. These functions exhibit a full-swing output voltage and the same supply and signal voltage, which suggests that the devices could be cascaded to create complex circuits. We also show that synaptic circuits based on only three homojunction devices can achieve reconfigurable spiking-timing-dependent plasticity and pulse-tunable synaptic potentiation or depression characteristics; the same function using complementary metal–oxide–semiconductor devices would require more than ten transistors. A homojunction device made from two-dimensional tungsten diselenide can be used to create circuits that exhibit multifunctional logic and neuromorphic capabilities with simpler designs than conventional silicon-based systems.

Electrostatically Reversible Polarity of Ambipolar α-MoTe2 Transistors.

Abstract: A doping-free transistor made of ambipolar α-phase molybdenum ditelluride (α-MoTe2) is proposed in which the transistor polarity (p-type and n-type) is electrostatically controlled by dual top gates. The voltage signal in one of the gates determines the transistor polarity, while the other gate modulates the drain current. We demonstrate the transistor operation experimentally, with electrostatically controlled polarity of both p- and n-type in a single transistor.

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

Abstract: Silicon nanowire transistors with Schottky-barrier contacts exhibit both n-type and p-type characteristics under different bias conditions. Polarity controllability of silicon nanowire transistors has been further demonstrated by using an additional polarity gate. The device can be configured as n-type or p-type by controlling the polarity gate voltage. This paper extends this approach by using three independent gates and shows its interest to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying different bias patterns to the three gates. Uncommitted logic gates can thus be configured to implement different logic functions, targeting either high-performance or low-leakage applications. Dual-threshold-voltage design is thereby achievable through the use of a wiring scheme on an uncommitted pattern. With the polarity controllability of the three-independent-gate device, a range of logic functions is also obtained by replacing VDD and GND by complementary input signals. Synthesis results of ISCAS’85 and VTR sequential benchmark circuits with these devices show, before place and route, comparable performance and 51% reduction of leakage power consumption compared to 22-nm low-standby-power FinFET technology.

Efficient Multiternary Digit Adder Design in CNTFET Technology

Abstract: This letter presents an efficient multiternary digit (trit) adder design in carbon nanotube field effect transistor technology. The adder is based on an efficient single-trit full-adder design with low-complexity encoder and reduced complexity carry-generation unit. Further, we optimize the number of encoder and decoder blocks required while putting together several single-trit full-adder units to realize a multitrit adder. Extensive HSPICE simulation results show roughly 79% reduction in power-delay product for three-trit adders and 88 $\hbox{\%}$ reduction in power-delay product for nine-trit adders in comparison to a direct realization.

Low Complexity Multiternary Digit Multiplier Design in CNTFET Technology

Abstract: This brief presents a multiternary digit (trit) multiplier design in carbon-nanotube field-effect transistor (CNTFET) technology using unary operators of multivalued logic. The proposed structure is based on the classical Wallace multiplier and includes a novel ternary multiplexer design requiring only a small number of CNTFETs. Two ternary full-adder configurations are also proposed based on an examination of the multiplier structure. In addition, the design includes a new single-trit multiplier which requires 67% less CNTFETs compared to a recent design. HSPICE simulations reveal low power-delay product for the proposed designs for different choices of drive strength. Furthermore, the designs are comparable to prior works with respect to noise margin.