Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >

Scaling the Si MOSFET: from bulk to SOI to bulk

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.

Beyond the conventional transistor

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

Describes the process fabrication and the electrical characteristics of an SOI (silicon-on-insulator) MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it. Device fabrication is simple and necessitates only a single additional mask and etch step, compared to standard SOI processing. The device shows evidence of volume inversion (inversion is observed not only in surface channels, but through the entire thickness of the silicon film). Because of the presence of two channels and because of reduced carrier scattering within the bulk of the silicon film, the transconductance of the 'gate-all-around' device is more than twice that of a conventional SOI device, and its subthreshold slope is nearly 60 mV/decade at room temperature. >

Silicon-on-insulator 'gate-all-around device'

A phenomenon called the MCCM (multistable charge-controlled memory) effect is observed in SOI MOS transistors working at lot temperatures. This MCCM effect essentially results in a controllable setting of the transistor threshold voltage by applying adequate voltage pulses (or up-down voltage sweeps) to one or more electrodes of the structure. A change in threshold voltage of several volts can be obtained. Stability on the order of hours and longer, depending on temperature and operational conditions, is observed. The physics behind the MCCM effect is discussed, and a simple analytical model is proposed. Some new applications based on the MCCM effect are briefly highlighted. >

The multistable charge-controlled memory effect in SOI MOS transistors at low temperatures

The total-dose radiation hardness of MOS devices is roughly inversely proportional to the square of the thickness of the oxide layers in contact with the silicon. In SOI (silicon-on-insulator) devices, the silicon layer sits on an oxide layer of typically 400 nm. It is proposed that a thin, gate-quality oxide can be realized at the front as well as the back of the devices, which should greatly enhance the radiation hardness. Double-gate devices (i.e. the same gate at the front and the back of the device) have been shown to have, at least theoretically, interesting short-channel and high transconductance properties. The only reported realization of such a device used a complicated, highly non-planar process (vertical devices) and left one edge of the device in contact with a thick oxide, which can be detrimental to rad-hard performances. Fabrication processes and device performances are described. >

Silicon-on-insulator 'gate-all-around' MOS device

The effects of the application of channel hot-carrier (CHC) stress applied at 42 K to SOI nMOS transistors are investigated. A reduction of the threshold voltage is observed for typical stressing conditions, while simultaneously the maximum transconductance increases. Similar changes can be obtained nearly immediately by applying a strong pulse into multiplication, i.e. by pulsing the drain voltage beyond the kink. At 4.2 K this 'low'-threshold-voltage (VT) state is metastable. These phenomena can be explained by considering hole trapping in the frozen-out film yielding a reduction of the depletion charge and an increase in the film potential. This results in a reduction of VT and of the transverse electric field. Due to the slow re-emission and to the steep forward diode characteristic, trapped charge will remain for a considerable time in the film, explaining the metastability of the hole-trapping-induced low-VT state at 4.2 K.

Metastable charge-trapping effect in SOI nMOSTs at 4.2 K

The dual-MOSFET structure proposed consists of two SOI nMOSFETs, T/sub 1/ and T/sub 2/, in series, but measured as a single device (T/sub 1/ to the source and T/sub 2/ to the drain) with a common gate electrode. The N/sup +/ region in between T/sub 1/ and T/sub 2/ is kept floating. This structure can confine the kink effect to the upper transistor T/sub 2/ and thus successfully keeps the lower transistor T/sub 1/ from undergoing pinch-off, impact ionization, and the kink effect. If the channel length of T/sub 1/ is longer than that of T/sub 2/, then T/sub 1/ will dominate the overall output characteristics of the device. As a result, the kink effect is eliminated from the overall output characteristics. This structure can also confine the parasitic bipolar effect only to the upper transistor T/sub 2/. Since the base hole current of T/sub 2/ will recombine in the common N/sup +/ region, it cannot reach the base region of the lower transistor T/sub 1/. Results of measurements and simulation are given. >

M.-H. Gao

Papers

Silicon-on-insulator 'gate-all-around device'

The multistable charge-controlled memory effect in SOI MOS transistors at low temperatures

Silicon-on-insulator 'gate-all-around' MOS device

Metastable charge-trapping effect in SOI nMOSTs at 4.2 K

Dual-MOSFET structure for suppression of kink in SOI MOSFETs at room and liquid helium temperatures