M. Iwaya

Bio: M. Iwaya is an academic researcher. The author has contributed to research in topics: Threshold voltage & Gate oxide. The author has an hindex of 1, co-authored 1 publications receiving 32 citations.

1200 V SiC IE-UMOSFET with low on-resistance and high threshold voltage

Abstract: A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at V g =25 V (E ox =3.2 MV/cm) and VG=20V (E ox =2.5 MV/cm), respectively, for the 3mm × 3mm device were 2.4 and 2.8 mΩcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mΩcm2 with a high Vth of 5.9 V.

Body PiN diode inactivation with low on-resistance achieved by a 1.2 kV-class 4H-SiC SWITCH-MOS

Abstract: Integration of SBD into SiC-MOSFET is promising to solve body-PiN-diode related problems known such as forward degradation and reverse recovery loss Particularly in lower breakdown-voltage-class SBD-integrated MOSFET, cell pitch reduction has a greater impact on inactivating the body-PiN-diode Here, we developed a novel device called an SBD-wall-integrated trench MOSFET (SWITCH-MOS), in which small cell pitch of 5pm was realized by utilizing trench side walls both for SBD and MOS channel with buried p+ layer The fabricated 12 kV SWITCH-MOS successfully suppressed the forward degradation under extremely high current density condition with low switching loss, low specific on-resistance, and low leakage current

Experimental and numerical demonstration and optimized methods for SiC trench MOSFET short-circuit capability

Abstract: This paper focused on the investigation of short-circuit capability and failure mechanism for the commercially available SiC trench MOSFETs. There are three failure mechanisms; (1) avalanche generation, (2) thermal runaway and (3) breakdown of gate oxide layer between gate-source electrodes by different short-circuit conditions. These are dependent upon the drain voltage and, especially in the high voltage region, the short-circuit capability could be improved by both the less negative gate-off voltage and cooling from top of the device without sacrifice of R ON A.

An Improved 4H-SiC Trench-Gate MOSFET With Low ON-Resistance and Switching Loss

Abstract: In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage ( ${V}_{\textsf {BR}}$ ). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time ( ${T}_{ \mathrm{\scriptscriptstyle ON}}$ ) and turn-off time ( ${T}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss ( ${E}_{\mathbf {SW}}$ ).

Comprehensive Characterization of the 4H-SiC Planar and Trench Gate MOSFETs From Cryogenic to High Temperature

Abstract: In this article, the static, dynamic, and short-circuit properties of 1.2-kV commercial 4H-SiC planar and trench gate metal–oxide–semiconductor field-effect transistors (MOSFETs) are compared and analyzed in a wide temperature range from 90 to 493 K. The temperature-dependent specific ON-resistance ( ${R}_{\text {sp}- \mathrm{\scriptscriptstyle ON}}$ ) and threshold voltage ( ${V}_{\text {th}}$ ) are analyzed in relation to the density of the interface state. The turn-on rise and turn-off fall times ( ${T}_{r}$ and ${T}_{f}$ ) and the corresponding energy loss ( ${E}_{r}$ and ${E}_{f}$ ) are extracted from a double-pulse test from cryogenic to high temperature and analyzed. The short-circuit capability of the two structures is studied at low temperature for the first time. The comprehensive comparison and analysis of the planar and trench gate MOSFET versus temperature in this work show the importance to study applications with SiC MOSFETs in a wide temperature range, especially for the cryogenic temperatures.

Experimental Demonstration on Superior Switching Characteristics of 1.2 kV SiC SWITCH-MOS

Abstract: A 1.2kV silicon carbide (SiC) SBD-wall-integrated trench MOSFET (SWITCH-MOS) had been proposed and fabricated in order to solve body-PiN-diode related problems such as bipolar degradation and reverse recovery loss. In this paper, switching characteristics of turn-on and turn-off of the SWITCH-MOS are investigated and discussed in comparison with conventional trench MOSFET structures with p+ region at trench gate bottom (IE-UMOSFET) and without the p+ region (named “device A” in this paper). The SWITCH-MOS shows an extremely small turn-on loss and turn-off loss because of the high $\boldsymbol{dV}/\boldsymbol{dt}$ and little reverse recovery current. In addition, it is found that the SWITCH-MOS exhibits smaller turn-off loss than “device A” at almost the same $\boldsymbol{dJ}/\boldsymbol{dt}$ , which means that drain surge voltage was suppressed effectively while keeping the smaller turn-off loss.