M.K. Iyer

Bio: M.K. Iyer is an academic researcher from Agency for Science, Technology and Research. The author has contributed to research in topics: Integrated circuit packaging & Chip-scale package. The author has an hindex of 6, co-authored 12 publications receiving 90 citations.

Thermal characterization of vias using compact models

Abstract: Thermal vias and balls are key elements in plastic ball grid array (PBGA) package thermal design as they enhance the package performance. Simulation is a versatile design optimization tool for characterizing the thermal vias and balls. However, the finer geometric details of the vias require excessive memory and modeling and simulation time. Different modeling concepts are being tried in the industry to include finer geometries in the package. This paper shows a methodology of developing compact thermal via models and validating the same with detailed models. The accuracy of compact thermal via models with respect to the detailed models has been determined using PBGA 352 as the test vehicle. It is found that the accuracy is within 3%. The simulation models of PBGA 352 have been validated by measurements and found that the accuracy of model is within 10%. Two and four layer PBGA 352s with different via configurations have been characterized with compact thermal via models, and design guidelines for PBGA 352 packages have been obtained.

Thermal design of heat spreader and analysis of thermal interface materials (TIM) for multi-chip package

Abstract: Industry demand for high power multi-chip packages is increasing to realize multifunctional compact systems. In line with industry requirements a multi-chip package suitable for high performance devices is developed. The package has 1296 I/Os. It is capable of handling 2 GHz signal speed and dissipating 75 W power with an external thermal solution. A concurrent design approach is adopted for the package design. Electrical, thermal, structural issues and assembly, and materials limitations are considered in developing this package. Package level thermal design challenges involve optimization of package structure and selection of stable thermal interface material. As a part of this project, a simulation model of the package along with the external thermal solution is developed and validated by measurements. The optimized heat spreader has been designed by performing a parametric study with the validated model. The type of thermal interface material (TIM) suitable to the package has also been identified by measurements. Desired thermal performance of the package has been achieved through design optimization of the package and selection of suitable TIM. Thermal modeling and measurement methodologies, validation and parametric study results are presented in the paper. Analysis of TIMs and measured thermal performance results of packages assembled with different type of TIMs are also discussed in the paper.

Compliant probes and test methodology for fine pitch wafer level devices and interconnects

Abstract: A compliant interposer sheet probe card and a method for testing a wafer or a wafer level package using the probe card are described. Test electronic circuits are connected on one side of a multi-layer substrate. A top side of a compliant interposer sheet is connected to an opposite side of the multi-layer substrate. A wafer or a wafer level package to be tested is contacted with pins on a bottom side of the compliant interposer sheet whereby the wafer or wafer level package can be tested.

Via design optimisation for high speed device packaging

Abstract: This paper presents the design and electrical characterization of a circular via hole applied to single and multi chip modules. A typical strip line-to-strip line configuration incorporating the via hole is designed, modelled and simulated using the Maxwell Strata mixed potential integration equation (MPIE)-based field solver. This configuration is modelled on a practical user-defined transmission line structure consisting of conductors of finite conductivity. We investigated the effects of three critical parameters, via hole diameter, ground plane opening and via height, on the frequency response. It is found that the via hole diameter should be minimized while the other two parameters should be maximized for better performance. This paper thus provides useful optimization criteria for circular vias, given the practical limitations of manufacturing technologies.

Device, unit, system and method for the magnetically-assisted assembling of chip-scale, and nano and micro-scale components onto a substrate

Abstract: A magnetically-assisted chip assembly unit for assembling at least one chip having a mounting surface and an attachment surface, wherein the attachment surface supports a magnetisable layer thereon and opposes said mounting surface, onto a substrate that has a corresponding chip mounting surface. The unit comprises a template wafer having at least one recess adapted to accommodate therein said chip; and a master wafer having at least one magnetisable element; wherein the template wafer is mounted on the master wafer and said magnetisable element is located at least proximate to the at least one recess such that the magnetisable element is capable of manipulating the chip into the recess, via its magnetisable layer when the magnetisable element is magnetized and generates a magnetic field. Once in the recess, the attachment surface of the chip faces at least a portion of the recess and the mounting surface of the chip faces an opening of the recess.

Thermal via placement in 3D ICs

Abstract: As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promising way of mitigating thermal issues by lowering the thermal resistance of the chip itself. However, thermal vias take up valuable routing space, and therefore, algorithms are needed to minimize their usage while placing them in areas where they would make the greatest impact. With the developing technology of three-dimensional integrated circuits (3D ICs), thermal problems are expected to be more prominent, and thermal vias can have a larger impact on them than in traditional 2D ICs. In this paper, thermal vias are assigned to specific areas of a 3D IC and used to adjust their effective thermal conductivities. The thermal via placement method makes iterative adjustments to these thermal conductivities in order to achieve a desired maximum temperature objective. Finite element analysis (FEA) is used in formulating the method and in calculating temperatures quickly during each iteration. As a result, the method efficiently achieves its thermal objective while minimizing the thermal via utilization.

Placement of thermal vias in 3-D ICs using various thermal objectives

Abstract: As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promising way of mitigating thermal issues by lowering the effective-thermal resistance of the chip. However, thermal vias take up valuable routing space, and therefore, algorithms are needed to minimize their usage while placing them in areas where they would make the greatest impact. With the developing technology of three-dimensional integrated circuits (3-D ICs), thermal problems are expected to be more prominent, and thermal vias can have a larger impact on them than in traditional two-dimensional integrated circuits (2-D ICs). In this paper, thermal vias are assigned to specific areas of a 3-D IC and used to adjust their effective-thermal conductivities. The method, which uses finite-element analysis (FEA) to calculate temperatures quickly during each iteration, makes iterative adjustments to these thermal conductivities in order to achieve a desired thermal objective and is general enough to handle a number of different thermal objectives such as achieving a desired maximum operating temperature. With this method, 49% fewer thermal vias are needed to obtain a 47% reduction in the maximum temperatures, and 57% fewer thermal vias are needed to obtain a 68% reduction in the maximum thermal gradients than would be needed using a uniform distribution of thermal vias to obtain these same thermal improvements. Similar results were seen for other thermal objectives, and the method efficiently achieves its thermal objective while minimizing the thermal-via utilization.

3D Floorplanning with Thermal Vias

Abstract: 3D circuits have the potential to improve performance over traditional 2D circuits by reducing wirelength and interconnect delay. One major problem with 3D circuits is that their higher device density due to reduced footprint area leads to greater temperatures. Thermal vias are a potential solution to this problem. This paper presents a thermal via insertion algorithm that can be used to plan thermal via locations during floorplanning. The thermal via insertion algorithm relies on a new thermal analyzer based on random walk techniques. Experimental results show that, in many cases, considering thermal vias during floorplanning stages can significantly reduce the temperature of a 3D circuit.

Development of liquid cooling techniques for flip chip ball grid array packages with High Heat flux dissipations

Abstract: In this paper, development of single-phase liquid cooling techniques for flip chip ball grid array packages (FBGAs) with high flux heat dissipations is reported. Two thermal test chips with different footprints, 12 mm/spl times/ 12 mm and 10 mm /spl times/10 mm, respectively, were used for high heat flux characterizations. A liquid-cooled aluminum heat sink with an area of 15 mm (L) /spl times/12.2 mm (W) populated by microchannels was designed and fabricated. The microchannel heat sink was assembled onto the chip, using a thermal interface material to reduce the contact thermal resistance at the interface. A variable speed pump was used to provide the pressure head for the liquid cooling loop. The measured thermal resistance results ranged from 0.44 to 0.32/spl deg/C/W for the 12-mm chip case and from 0.59 to 0.44/spl deg/C/W for the 10-mm chip case, both under flowrates ranging from 1.67/spl times/10/sup -6/ m/sup 3//s to 1.67/spl times/10/sup -5/ m/sup 3//s. An analytical model of the flow and heat transfer in microchannel heat sinks is also presented. Computational predictions agree with the measurements for pressure drop within 15% and thermal resistances within 6%. The analytical results indicate that thermal interface resistance becomes a key limitation to maximizing heat removal rate from electronic packages.