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M. L. Keote

Bio: M. L. Keote is an academic researcher from Yeshwantrao Chavan College of Engineering. The author has contributed to research in topics: Adiabatic circuit & Inverter. The author has an hindex of 2, co-authored 2 publications receiving 11 citations.

Papers
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Proceedings ArticleDOI
01 Oct 2015
TL;DR: Improved structure for efficient charge recovery logic is presented and a comparative study among the inverter and basic gates at transition frequency varying from 50MHz to 400MHz is presented.
Abstract: In this paper Improved structure for efficient charge recovery logic is presented. In order to optimize the power dissipation of digital systems, low-power analysis should be applied throughout the design process from system level to process level. Further NAND and NOR gates have been implemented with efficient charge recovery logic (ECRL) and Proposed efficient charge recovery logic. Paper presents a comparative study among the inverter and basic gates at transition frequency varying from 50MHz to 400MHz. The proposed circuits attain large energy saving compared with conventional circuits. The circuits are simulated using 180nm technology nodes.

12 citations

Proceedings ArticleDOI
01 Sep 2016
TL;DR: In this article, the implementation of flip flops and 3-bit binary up counter using Modified Quasi State Energy Recovery Logic (MQSERL) is presented, where two phase power clock supply and 1800 phase shifted signal is used in MQSERL to minimize switching activities of circuit node.
Abstract: This paper presents implementation of flip flops and 3 bit binary up counter using Modified Quasi State Energy Recovery Logic (MQSERL). Two phase power clock supply and its 1800 phase shifted signal is used in MQSERL to minimize switching activities of circuit node. Initially circuits such as INVERTER, NAND, NOR, XOR and 2:1 multiplexer have been designed using MQSERL style and conventional CMOS logic. Comparative analysis has been done by computing power dissipation, propagation delay and Power Delay Product to validate the functionality of proposed MQSERL. Further D flip flop with preset and clear terminal have been designed using three input NAND gate and then 3 bit binary up counter using both the logic styles. All the circuits are simulated using 180nm tanner technology and at operating voltage of 1.8v. Clock frequency for MQSERL is set at 100MHz and input signal at 50 MHz. The MQSERL D flip Flop is 82.21% and 3 bit binary Counter is 94.40% power efficient over conventional CMOS logic.

2 citations

Proceedings ArticleDOI
17 May 2023
TL;DR: In this paper , it has been established after careful examination that the majority of accidents and in fatalities as a result of inadequate communication with the appropriate medical authorities and the following lack of urgent medical care.
Abstract: The average number of vehicles on the road worldwide has increased as cars and other vehicles become more and more accessible. Our lives are now easier because of the technology and infrastructure that are developing quickly. The advent of technology has also enhanced the risks associated with traffic and Regular traffic accidents result in a number of accidents on this dynamic planet and significant loss of life and property due to inadequate emergency facilities. Accident victims suffer greatly and lose significant time and money as a result. It has been established after careful examination that the majority of accidents and in fatalities as a result of inadequate communication with the appropriate medical authorities and the following lack of urgent medical care. There are many deaths as a result of inadequate crisis management. As a result, this research study intends to provide crisis administrations to the person who meets with an accident as soon as time permits
Proceedings ArticleDOI
16 Mar 2022
TL;DR: In this article , a portable insulin box which provides low temperature using solar power has been proposed and the temperature of the insulin box can be monitored by the temperature sensor which is placed on the box.
Abstract: As per the research, the number of diabetic patients in India is very high which makes it the second most diabetes affected country in the world. The insulin pen is largely used to limit the effect of this disease. The insulin should be stored at low temperature and for this purpose a portable insulin box which provides low temperature using solar power has been proposed. The temperature of the insulin box can be monitored by the temperature sensor which is placed on the box.

Cited by
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Proceedings ArticleDOI
01 Jun 2017
TL;DR: Experimental evaluations show that this work exploits the accomplishments of these complementary areas and, realize fully reversible adiabatic circuits which have a substantially smaller power consumption than conventional circuit technologies.
Abstract: Today, energy saving is a major design target, since the number of mobile-or power-independent devices is increasing. These devices should operate as long as possible with one battery charge. Especially for designs where speed is of secondary importance, adiabatic circuits are a promising alternative. These kind of circuits are rather slow but extremely energy efficient. However, the full potential of adiabatic circuits can only be fully exploited if computations are conducted in a reversible fashion. This is not the case for conventional circuits which are usually composed of non-reversible gates such as AND, OR, etc. At the same time, design methods for so-called reversible circuits received significant interest — mainly motivated by emerging technologies such as quantum computation or encoder design. In this work, we exploit the accomplishments of these complementary areas and, realize fully reversible adiabatic circuits. Experimental evaluations show that this yields circuits which have a substantially smaller power consumption than conventional circuit technologies.

17 citations

Journal ArticleDOI
TL;DR: A power efficient design of synchronous counters is proposed that reduces the power consumption due to clock distribution for different flip-flops and offers high reliability and the power reduction is more significant for wide-bit counters.

15 citations

Journal ArticleDOI
TL;DR: In this article, a PFAL logic circuit is used to simulate various logic gates and compare the effectiveness in terms of average power dissipation and delay at different frequencies at different frequency ranges.
Abstract: With the continuous scaling down of technology in the field of integrated circuit design, low power dissipation has become one of the primary focuses of the research. With the increasing demand for low power devices, adiabatic logic gates prove to be an effective solution. This paper briefs on different adiabatic logic families such as ECRL (Efficient Charge Recovery Logic), 2N-2N2P and PFAL (Positive Feedback Adiabatic Logic), and presents a new proposed circuit based on the PFAL logic circuit. The aim of this paper is to simulate various logic gates using PFAL logic circuits and with the proposed logic circuit, and hence to compare the effectiveness in terms of average power dissipation and delay at different frequencies. This paper further presents implementation of C17 and C432 benchmark circuits, using the proposed logic circuit and the conventional PFAL logic circuit to compare effectiveness of the proposed logic circuit in terms of average power dissipation at different frequencies. All simulations are carried out by using HSPICE Simulator at 65 nm technology at different frequency ranges. Finally, average power dissipation characteristics are plotted with the help of graphs, and comparisons are made between PFAL logic family and new proposed PFAL logic family.

10 citations

Proceedings ArticleDOI
01 Jan 2016
TL;DR: This paper aims at comparing the effectiveness of proposed adiabatic logic circuit, in terms of power dissipation, over other adiABatic logic families by simulating different logic gates using these logic families.
Abstract: With the continuously growing quest for miniaturization of circuit technology, one of the prime focuses of the research has shifted in the direction of ultra low power circuit designs. Over the years, adiabatic circuit designs have been studied and found to be effective in achieving low power in VLSI circuits. This paper briefs some of the adiabatic logic families such as ECRL, 2N-2N2P and PFAL. And presents a new adiabatic logic circuit based on PFAL logic family. This paper aims at comparing the effectiveness of proposed adiabatic logic circuit, in terms of power dissipation, over other adiabatic logic families by simulating different logic gates using these logic families. All the simulations are done using HSPICE Simulator at 65nm technology at different frequency range. Comparative results are presented by different bar graphs plotted at different frequencies, which shows least power dissipation for the proposed logic circuit.

7 citations

Book ChapterDOI
01 Jan 2020
TL;DR: The result shows the significant reduction in power dissipation up to 26, 36, 16, 59, 73, 99% for inverter, NAND gate, NOR gate, EXOR gate, 2:1 MUX, and full adder circuits with adiabatic logic comparatively CMOS within specified frequency range of 1 kHz to 1 MHz.
Abstract: This paper presents the comparative analysis of average power dissipation for conventional CMOS and different adiabatic logic techniques like efficient charge recovery logic (ECRL) and positive feedback adiabatic logic (PFAL) based digital circuits like inverter, NAND, NOR, 2:1 MUX, EXOR, and full adder. These circuits are based on reversible logic that works on AC power supply which can be trapezoidal or sinusoidal voltage source. The analysis of average power and delay is carried out at 180, 90, and 45 nm technology files for different frequencies. The result shows the significant reduction in power dissipation up to 26, 36, 16, 59, 73, 99% for inverter, NAND gate, NOR gate, EXOR gate, 2:1 MUX, and full adder circuits, respectively with adiabatic logic comparatively CMOS within specified frequency range of 1 kHz to 1 MHz and also manifests till what extent the power can be reduced so as to avoid degradation in performance. The design and simulation are performed on cadence virtuoso EDA tool.

3 citations