M. Lipinski

Bio: M. Lipinski is an academic researcher from Infineon Technologies. The author has contributed to research in topics: Low-power electronics & CMOS. The author has an hindex of 1, co-authored 1 publications receiving 45 citations.

Competitive and cost effective high-k based 28nm CMOS technology for low power applications

Abstract: In this paper, we present a cost-effective 28nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm2, and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28nm from 45nm technology. Our high-density SRAM bit-cell (area= 0.120mm2) has a demonstrated Static Noise Margin (SNM) of 213mV at 1V. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28nm LP poly/SiON reference [3]. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor (AVT∼2mV.um) versus our previously-reported result [2]. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k∼2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology.

Process Technology Variation

Abstract: Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Abstract: Reducing static random-access memory (SRAM) operational voltage (Vmin) can greatly improve energy efficiency, yet SRAM Vmin does not scale with technology due to increased process variability. Assist techniques have been shown to improve the operation of SRAM, but previous investigations of assist techniques at design time have either relied on static metrics that do not account for important transient effects or make specific assumptions about failure distributions. This paper uses importance sampling of dynamic failure metrics to quantify and analyze the effect of different assist techniques, array organization, and timing on Vmin at design time. This approach demonstrates that the most effective technique for reducing SRAM Vmin is the negative bitline write assist, resulting in a Vmin of 600 mV for a 28-nm LP process in the typical corner.

Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies

Abstract: Large scale BTI data was collected on discrete MG/HK devices to discuss modeling challenges related to BTI induced variability. A fast, parallel BTI testing procedure is introduced. This utilizes the PCI card characterization methodology to highlight a close link between BTI variability and RDF, and to discuss the impact of BTI recovery and wafer-to-wafer variation on the BTI statistics. We demonstrate a correlation between time-zero VT and ΔVT and illustrate the minor impact of BTI induced variability on post-stress VT distributions relevant for modeling the circuit aging.

A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization

Abstract: Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology A 0040 $\mu \text{m}^{2}$ 6T SRAM bitcell is designed for high density (HD), and 0049 $\mu \text{m}^{2}$ for high performance (HP) The various SRAM assist schemes are explored to evaluate the power, performance, and area (PPA) gain, and the figure-of-merit (FOM) is induced by the minimum operating voltage ( $V_{\mathrm{ MIN}}$ ) and assist overheads The dual-transient wordline scheme is proposed to improve the $V_{\mathrm{ MIN}}$ by 475 mV for the 128 Mb 6T-HP SRAM The suppressed bitline scheme with negative bitline improves the $V_{\mathrm{ MIN}}$ by 135 mV for the 128 Mb 6T-HD SRAM The FOM of PPA gain evaluates the optimum SRAM assist for the different bitcells based on the applications

A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs

Abstract: In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device $V_{T}$ retargeting has been proposed for improving the minimum operating voltage ( $V_{\min }$ ) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%–30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a $6\sigma $ yield target and an isoarea of SRAM bitcells, $V_{\min }$ of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed $V_{T}$ retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is $2.6\times $ lower than LFET bitcells.