Considerable research has been done in the area of bus-encoding techniques, for either power minimization or cross-talk elimination in system-level buses, but not both together. We propose No Adjacent Transition (NAT) coding scheme, a bus encoding technique that simultaneously reduces power consumption and eliminates cross-talk. NAT-encoding and decoding algorithms are proposed and an analytical study of power dissipation is presented.

A bus encoding technique for power and cross-talk minimization

A survey of encoding techniques for reducing data-movement energy

In many digital processors, the power dissipation in the bus is a major part of the total chip power dissipation. For CMOS circuits most power is dissipated as a dynamic power for charging and discharging node capacitances. In non deep sub-micron technology, these capacitances are mainly the substrate capacitances of the bus wires where as in deep sub-micron technology inter wire capacitance also contribute to total capacitance. The main objective of this paper is to explain a new algorithm called Bus Regrouping Method to reduce coupling transitions. As a consequence the power dissipation due to the coupling capacitance or inter wire capacitance in deep sub-micron technology is optimized.

Bus Regrouping method to Optimize Power in DSM Technology

In deep-submicron technology (DSM), minimizing the propagation delay and power dissipation on buses is the most important design objective in system-on-chip (SOC) design In particular, the coupling effects between wires on the bus that can cause serious problems such as cross-talk delay, noise and power dissipation Most of the researchers have concentrated either on minimizing the power dissipation or minimizing crosstalk delay In this paper, the authors propose a technique for energy efficient data transmission for on-chip buses and evaluate the effectiveness of our technique by using SPEC 95 benchmarks suit The authors show that our technique achieves 35% of energy savings over the un-encoded data transmission on the data bus

Energy Efficient Spatial Coding Technique for Low Power VLSI Applications

In CMOS VLSI circuits, the dynamic power dissipation contributes a significant fraction in the overall power dissipation. Hence, the main target of VLSI designers is to minimize the switching activity on the on-chip bus lines. In this paper, the authors propose a novel bus encoding technique which minimizes both self and coupling transition activity to curtail the global power dissipation. The performance of the proposed coding scheme has been tested on various SPEC'95 benchmarks and found that with respect to unencoded data, an average reduction of 28% and 26% with respect to self and coupling energies in the total power dissipation is achieved. The hardware, used for encoding and decoding purposes, has been designed using Magmacopytools.

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Coding for Minimizing Energy in VLSI Interconnects

Designing chips for lower power applications is one of the most important challenges faced by the VLSI designers. Since the power consumed by I/O pins of a CPU is a significant source of power consumption, work has been done on developing encoding schemes for reducing switching activity on external buses. In this paper we propose a new coding technique, namely, the Dynamic Coding Scheme, for low-power data bus. Our method considers two logical groupings of the bus lines, each being a permutation of the bus lines, and dynamically selects that grouping which yields the minimum number of transitions.

M. Madhu

Papers

Dynamic coding technique for low-power data bus