M. Ming-Tak Leung

Bio: M. Ming-Tak Leung is an academic researcher from Texas Instruments. The author has contributed to research in topics: Ternary Golay code & Differential amplifier. The author has an hindex of 3, co-authored 3 publications receiving 412 citations.

Improved sense-amplifier-based flip-flop: design and measurements

Abstract: Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output stage latch topology that significantly reduces delay and improves driving capability. The performance of this flip-flop is verified by measurements on a test chip implemented in 0.18 /spl mu/m effective channel length CMOS. Demonstrated speed places it among the fastest flip-flops used in the state-of-the-art processors. Measurement techniques employed in this work as well as the measurement set-up are discussed in this paper.

Reduced complexity sequence detection for high-order partial response channels

Abstract: Detector hardware complexity of high-order partial response magnetic read channels is a major obstacle to high data rate operation and reduced area and power consumption. The method presented here reduces the complexity of single-step and two-step implementations of the Viterbi detector by applying a distance-enhancing code that eliminates some states from the code trellis. The complexity of the detector is further reduced by eliminating less-probable branches from the trellis. This is accomplished by a simple control mechanism that uses the signs of the consecutive input samples. The reduced set of add-compare-select (ACS) units is dynamically assigned to the detector states, decreasing the complexity of the Viterbi detector by roughly 50%. This method is demonstrated on high-order partial response systems with the E/sup 2/PR4 target and an 11-level/32-state target. The simulation results show negligible bit error rate (BER) degradation for signal-to-noise ratios In the range of operation of contemporary disk drive read channels.

Rate 8/9 sliding block distance-enhancing code with stationary detector

Abstract: A new distance-enhancing code for partial-response magnetic recording channels eliminates most frequent errors, while keeping the two-step code trellis time invariant. Recently, published trellis codes either have lower code rates or result in time-varying trellises with a period of nine, thus requiring a higher complexity of detectors and code synchronization. The new code introduces dependency between code words in order to achieve the same coding constraints as the 8/9 time-varying maximum transition runlength (TMTR) code, with the same code rate, but resulting in a trellis that has a period of 2. This code has been applied to the E/sup 2/PR4 and a 32-state generalized partial response (GPR) ISI target. The resulting two-step trellises have 14 and 28 states, respectively. Coding gain is demonstrated for both targets in additive white Gaussian noise.

A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards

Abstract: To protect security devices such as smart cards against power attacks, we propose a dynamic and differential CMOS logic style. The logic operates with a power consumption independent of both the logic values and the sequence of the data. Consequently, it will not reveal the sensitive data in a device. We have built a set of logic gates and flip-flops needed for cryptographic functions and compared those to Static Complementary CMOS implementations.

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time

Abstract: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time

Yield and speed optimization of a latch-type voltage sense amplifier

Abstract: A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage. The input DC level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input DC bias voltage. A figure of merit indicates that an input dc level of 0.7 V/sub DD/ is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input DC voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.

1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

Abstract: We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least significant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.

CMOS Imager With 1024 SPADs and TDCs for Single-Photon Timing and 3-D Time-of-Flight

Abstract: We present a CMOS imager consisting of 32×32 smart pixels, each one able to detect single photons in the 300-900 nm wavelength range and to perform both photon-counting and photon-timing operations on very fast optical events with faint intensities. In photon-counting mode, the imager provides photon-number (i.e, intensity) resolved movies of the scene under observation, up to 100 000 frames/s. In photon-timing, the imager provides photon arrival times with 312 ps resolution. The result are videos with either time-resolved (e.g., fluorescence) maps of a sample, or 3-D depth-resolved maps of a target scene. The imager is fabricated in a cost-effective 0.35-μm CMOS technology, automotive certified. Each pixel consists of a single-photon avalanche diode with 30 μm photoactive diameter, coupled to an in-pixel 10-bit time-to-digital converter with 320-ns full-scale range, an INL of 10% LSB and a DNL of 2% LSB. The chip operates in global shutter mode, with full frame times down to 10 μs and just 1-ns conversion time. The reconfigurable imager design enables a broad set of applications, like time-resolved spectroscopy, fluorescence lifetime imaging, diffusive optical tomography, molecular imaging, time-of-flight 3-D ranging and atmospheric layer sensing through LIDAR.