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Author

M. Moydudy

Bio: M. Moydudy is an academic researcher. The author has contributed to research in topics: Energy (signal processing) & Capacitance. The author has an hindex of 1, co-authored 1 publications receiving 6 citations.

Papers
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Proceedings ArticleDOI
01 Mar 2017
TL;DR: In this article, a new capacitor array structure which is both energy and area efficient is presented for a 4-bit successive approximation register (SAR) analog-to-digital converter (ADC).
Abstract: A new capacitor array structure which is both energy and area efficient is presented for a 4 bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed circuit consumes zero energy in the second and third comparison cycles. Significant lowering of energy in the different charge redistribution steps is ensured by applying different voltages in the switching scheme of the various comparison cycles. Besides energy saving to the extent of 98%, a 75% reduction in capacitance is achieved compared to the conventional method.

6 citations


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Proceedings ArticleDOI
01 Mar 2019
TL;DR: A novel technique that combines the advantageous features of hybrid and junction splitting technique is presented for realization of a very high energy efficient SC SAR ADC which achieves a 50% reduction in unit capacitance requirements over the conventional one.
Abstract: A novel technique that combines the advantageous features of hybrid and junction splitting technique is presented for realization of a very high energy efficient SC SAR ADC. The hybrid capacitor switching scheme is very energy efficient in which the first three comparison cycles do not consume any energy. The junction splitting technique involves appending capacitors as each bit is successively being determined by the system. The present paper combines these two features to realize an SC SAR ADC which is more energy efficient than either of the two. The method provides energy savings as well as unit capacitor saving. Thus the method becomes one of the most energy efficient switching schemes among its peers. It achieves a 50% reduction in unit capacitance requirements over the conventional one.

4 citations

Journal ArticleDOI
TL;DR: A combinational method, based on hybrid and junction splitting techniques, is used to realize a 4 bit high energy efficient SC SAR ADC.
Abstract: A combinational method, based on hybrid and junction splitting techniques, is used to realize a 4 bit high energy efficient SC SAR ADC. The hybrid switching scheme is very energy efficient in which the first three comparison cycles do not consume any energy. In junction split technique, the total value of capacitors does not remain constant. Rather capacitors are appended as bits are being determined successively. The present method combines the features of these two methods to realize an even more energy efficient SC SAR ADC. Reset energy, in some cases, can seriously impact the overall efficiency of a SC SAR ADC. A study has been made about the normal reset energy and two step reset energy for the different cases. A table has been drawn to show the overall energy efficiency for normal conversion, conversion with single step reset and lastly conversion with two step reset for all the architectures.

2 citations

Journal ArticleDOI
TL;DR: In this paper, an energy and area efficient switching scheme for a 4-bit charge redistribution switch capacitor (SC) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed.
Abstract: An energy and area efficient switching scheme for a 4-bit charge redistribution switch capacitor (SC) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. Single and two step reset energies are also considered for calculations of energy efficiencies. The designed architecture consumes zero energy in the first and third comparison cycles where energy consumptions are relatively high, leading to high energy efficiency. It is seen that switching energy, without reset, is as high as 99%. With reset energy taken into consideration, energy savings become 98.44% and 98.4% for single and two step reset methods respectively. Thus the method becomes one of the most energy efficient switching schemes recently presented by different researchers. The scheme also achieves a 75% reduction in unit capacitance requirements over the conventional method. It is also seen that both INL and DNL of the proposed method are better than several other established methods.
Book ChapterDOI
01 Jan 2021
TL;DR: An energy and area efficient switching scheme for a 4-bit charge redistribution switch capacitor (SC) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed in this article.
Abstract: An energy and area efficient switching scheme for a 4-bit charge redistribution switch capacitor (SC) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. It is based on conventional binary search algorithm. The charge redistribution type architecture implemented in the proposed scheme is fully differential in nature, hence the operation of the two sides is complementary. The proposed switching technique consumes zero energy in the first and third comparison cycles. It It is seen that the switching energy saving is as high as 99%. The method thus becomes one of the most energy efficient switching schemes recently presented by different researchers. Besides such an enormous savings in energy, it also achieves a 75% reduction in unit capacitance requirements over the conventional method. The common mode voltage variations at the comparator inputs have been studied and it is seen that the same is better than either the modified merged or hybrid method.
Proceedings ArticleDOI
25 Jun 2021
TL;DR: In this paper, a binary search analog-to-digital converter based on sub-ADC was proposed. But the performance of the proposed ADC is limited by the number of comparators.
Abstract: This paper presents a binary search analog to digital converter based on sub-ADC scheme in which the 16-bit architecture is split into four stages and the whole architecture uses only N comparators instead of (2N-1) comparators. The proposed design enables comparators in sequential manner using asynchronous logic and achieves low power and less chip area with high conversion speed. The proposed binary search ADC has been implemented in 180 nm CMOS process and consumes 8mW of power when operated at 1.8 V. The transient result verifies that the proposed design achieves the conversion rate of 87.26 MSPS and its spectrum specifies the ENOB, SNDR and SFDR as 11.3 bit, 23 dB and 25 dBc respectively with 0.158pJ/conv-step of Walden figure of merit (FOM w ) at sampling frequency of 20MSPS.