The multicellular structure of biological organisms and the interpretation in each of their cells of a chemical program (the DNA string or genome) is the source of inspiration for the Embryonics (embryonic electronics) project, whose final objective is the design of highly robust integrated circuits, endowed with properties usually associated with the living world: self-repair and self-replication. In this article, we provide an overview of our latest research in the domain of the self-replication of processing elements within a programmable logic substrate, a key prerequisite for achieving system-level fault tolerance in our bio-inspired approach.

https://www-users.york.ac.uk/~gt512/Publications/2007/ACM07-Tempesti.pdf

Self-replicating hardware for reliability: The embryonics project

Except where reference is made to the work of others, the work described in this thesis is my own or was done in collaboration with my advisory committee. This dissertation does not include proprietary or classified information. Permission is granted to Auburn University to make copies of this thesis at its discretion, upon the request of individuals or institutions and at their expense. Nanometer CMOS VLSI circuits are highly sensitive to soft errors due to environmental causes such as cosmic radiation and high-energy particles. These errors are random and not related to permanent hardware faults. Their causes may be internal caused in microelectronic circuits when high energy particles strike at sensitive regions of the silicon devices. The soft error rate (SER) estimation analytically predicts the effects of cosmic radiation and high-energy particle strikes in integrated circuit chips by building SER models. An accurate analysis requires simulation using circuit netlist, device characteristics, manufacturing process and technology parameters, and measurement data on environmental radiation. Experimental SER testing is expensive and analytical approaches are, therefore, beneficial. We model neutron-induced soft errors using two parameters, namely, occurrence rate and intensity. Our new soft error rate (SER) estimation analysis propagates occurrence rate and intensity as the width of single event transient (SET) pulses, expressed as v a probability and a probability density function, respectively, through the circuit. We consider the entire linear energy transfer (LET) range of the background radiation which is available from measurement data specific to the environment and device material. Soft error rates are calculated for ISCAS85 benchmark circuits in the standard units, failure in time (FIT, i.e., failures in 10 9 hours). In comparison to the reported SER analysis results in the literature, our method considers several more relevant factors including sensitive regions, circuit technology, etc., which may influence the SER. Our simulation results for ISCAS85 benchmark circuits show similar trend as other reported work. For example, our soft error rate results for C432 and C499 considering ground-level environment are 1.18×10 3 FIT and 1.41×10 3 FIT, respectively. Although no measured data are available for logic circuits, SER for 0.25µ and 0.13µ 1M-bit SRAMs have been reported in the range 10 4 to 10 5 FIT, and for 0.25µ 1G-bit SRAM around 4.2 × 10 3 FIT. We also discuss the factors that may cause several orders of magnitude difference in our results and certain other logic analysis methods. The CPU …

Soft Error Rate Determination For Nanometer CMOS VLSI Circuits

With operational faults becoming the dominant cause of failure modes in modern VLSI, widespread deployment of on-line test technology has become crucial. In this paper, we present a non-concurrent on-line testing technique via scan chains. We discuss the modifications needed in the design so that it can be tested on-line using our technique. We demonstrate our technique on a case study of a pipelined 8 x 8 multiply and accumulate unit. The case study shows that our technique is characterized by high error coverage, moderate hardware overhead, and negligible time redundancy.

Non-Concurrent On-Line Testing Via Scan Chains

Code checkers that monitor the outputs of a system can detect both permanent and transient faults. We present two novel architectures of embedded self-testing checkers for low-cost and cyclic arithmetic codes, one based on code word generators and adders, the other based on code word accumulators. In these schemes, the code checker receives all possible code words but one, irrespective of the number of different code words that are produced by the circuit under check (CUC). So any code checker can be employed that is self-testing for all or a particular subset of code words, and the structure of the code checker need not be tailored to the set of code words produced by the CUC. The proposed code word generators and accumulators are built from simple standard hardware structures, counters and end-around-carry adders. They can also be utilized in an off-line BIST environment as pattern generators and test response compactors.

Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes

The evolution of Artificial Intelligence has passed through many phases over the years, going from rigorous mathematical grounding to more intuitive bio-inspired approaches. However, to date, it has failed to pass the Turing test. A popular school of thought is that stagnation in the 1970s and 1980s was primarily due to insufficient hardware resources. However, if this had been the only reason, recent history should have seen AI advancing in leaps and bounds – something that is conspicuously absent. Despite the abundance of AI algorithms and machine learning techniques, the state of the art still fails to capture the rich analytical properties of biological beings or their robustness. Moreover, recent research in neuroscience points to a radically different approach to cognition, with distributed divergent connections rather than convergent ones. This leads one to question the entire approach that is prevalent in the discipline of AI today, so that a re-evaluation of the basic fabric of computation may be in order.

In practice, the traditional solution for solving difficult AI problems has always been to throw more hardware at it. Today, that means more parallel cores. Although there are a few parallel hardware architectures that are novel, most parallel architectures – and especially the successful ones – simply combine Von Neumann style processors to make a multi-processor environment. The drawbacks of the Von Neumann architecture are widely published in literature. Regardless, even though the novel architectures may not implement non-Von-Neumann style cores, computation is still based on arithmetic and logic units (ALU). The aim of this research is to explore the possibility of whether an alternative hardware architecture inspired from the biological world, and entirely different from traditional processing, may be better suited for implementing intelligent behaviour while also exhibiting robustness.

M. Nicolaidis

Papers

Online VLSI Testing