In the present global scenario, social distancing is an inevitable one. The need for social distancing and advancements of technology to facilitate the patients and doctors around the world mandated the telemedicine and remote monitoring of patience details as the pivotal way to diagnose the disease. In this, it is essential to transmit the patient’s information such as X-ray and scan images of them to the doctor in the remote location. Preventing the medical data from the technological adversaries is the need of the hour. Infinitesimal attacks in medical images may cost human lives. This work proposes a lightweight, secure medical image encryption scheme for the remote monitoring of health data. The proposed encryption scheme uses computationally less complex weighted shift approximate adder (WSAA)–based encryption logic. The scheme uses a 256-bit key for the encryption process that strengthens the encryption and robust against various attacks. The proposed encryption scheme deploys the WSAA for diffusing the pixel values. A unique way of key distribution for pixel-wise encryption within the image is proposed that avoids the need for separate logic for the pixel-wise confusion. The proposed Encryption scheme is evaluated for its entropy and horizontal, vertical, diagonal correlation, histogram, key space, and sensitivity. Experimental results affirm that the proposed scheme significantly good with less computational complexity. The peak signal-to-noise ratio (PSNR) value of the decrypted image is infinity, and this matches the ideal requirement of the medical encryption scheme.

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A Novel Random Error Approximate Adder-Based Lightweight Medical Image Encryption Scheme for Secure Remote Monitoring of Health Data

This research article proposes high-performance square-root carry select adder (SQRT CSLA) architectures with high speed, area and energy efficiency when compared to the existing SQRT CSLA architectures. The first proposed method uses an optimized design of binary to excess-1 converter (BEC)-based SQRT CSLA by incorporating a carry enable binary to excess-1 converter (CEBEC) design that exploits a new logic optimization on the carry propagation path to improve speed of operation, area and energy efficiency. The second proposed method is an optimized design of the regular SQRT CSLA by employing the carry enable and add-one ripple carry adder (ARCA) architectures to decrease the number of gates. Simulation results show that the proposed CEBEC SQRT CSLA offers a savings of 22.81%, 9.95%, 7.95% and 3.98% on area, 14.50%, 5.21%, 3.72% and 3.11% in power consumption and offers 6.78%, 15.46%, 6.57% and 3.83% lesser delay, 20.33%, 19.92%, 10.09% and 6.89% lesser PDP, 28%, 23.85%, 13.78% and 7.58% lesser ADP than the existing regular, BEC SQRT CSLA, SQRT CSLA1 and SQRT CSLA2 architectures. The proposed ARCA SQRT CSLA architecture exhibits 9.26%, 17.71%, 9.06% and 6.39% lesser delay than the existing regular, BEC SQRT CSLA, SQRT CSLA1 and SQRT CSLA2 architectures.

High-Performance Carry Select Adders

Logistics management inventory model based on 5G Network and Internet of Things system

Full Adder cell is the main building block of larger arithmetic circuits and often is placed along their critical path. Therefore, it is a vital task to design high-performance and low-energy Full ...

High-performance and low-energy approximate full adder design for error-resilient image processing

In this work we introduce a framework to support design decisions for heterogeneous IoT platforms and devices. The framework methodology as well as the development of software and hardware models are outlined. Specific factors that affect the performance of device are identified and formulated in a metric form. The performance aspects are embedded in a flexible and scalable framework for decision support. An indicative experimental setup investigates the applicability of the framework for a specific functional block. The experimental results are used to assess the significance of the framework under development.

Identifying Metrics for an IoT Performance Estimation Framework

High performance compact energy efficient error tolerant adders and multipliers for 16-bit image processing applications

Efficient utilization of on-chip Static Random Access Memory (SRAM) space is more important on processor core design in modern Field Programmable Gate Array (FPGA) based Digital Signal Processing (DSP) applications. In the proposed High-performance Approximate Single Port (HASP) SRAM architecture, a significant amount of data is stored to achieve high performance. The constraints involved with high performance are counterbalanced to provide high accuracy, high speed, low power and area efficiency. In the proposed High-performance Approximate Sub-Bank Dual Port (HASBDP1 and HASBDP2) memory architectures, HASP has been employed and modified to work as a True DP SRAM with energy and area efficiency. The performance of the proposed memories is investigated by comparing its speed, area and power with those of the existing approaches. The proposed HASP SRAM provides 14.99% less power consumption and thirteen numbers of logic elements savings in the resource utilization than the existing conventional SP SRAM. By considering the design metrics, the proposed HASBDP SRAMs outperform than the conventional TDP and sub-bank DP SRAMs approaches. The proposed HASBDP2 exhibits 29.09%, 22.37% higher PSNR and 32.94%, 28.48% higher SSIM than the truncated least significant bit and static segment on-chip approximate memories respectively.

High Performance Approximate Memories for Image Processing Applications

In the modern applications there are lot of computing resources starting from Central Processing Units, Networks on Chips to Field Programmable Gate Arrays, each catering various types of operations. These factors motivate this research, to exploit 16-bit High Performance Variable Accuracy Reconfigurable Adder (HPVARA) and High Performance Error Tolerant Adder (HPETA-III) which are used extensively in many computing architectures for hybrid and error tolerant applications. The simulation based research outcome of the proposed HPVARA structure shows 13.69%, 15.95%, 9.82%, 22.53%, 13.56% improved Area Delay Product and 12.15%, 11.86%, 8.74%, 15.12%, 14.96% improved Power Delay Product with the computational outputs varying between 91.788% and 100% with the input operand pair compared to the existing ACA-I, ACA-II, GDA, VARA4 and conventional CSLA architectures. The second part of the research is focused on optimizing the design of the High Performance Error Tolerant Adder (HPETA-III). The proposed HPETA-III design performance is evaluated to offer a savings of logic gate count ranges from 268, 212, 173, 184, 196, 172, 68, 76, 60, 21 with respect to CSLA, VARA4, HSSSA, SAET-CSLA, ETCSLA, HSETA, HPETA-I, HPETA-II, CEETA, CEETA1 architectures respectively and also interesting results have been observed with reduced power, delay, PDP and ADP.

M. Peer Mohamed

Papers

High performance compact energy efficient error tolerant adders and multipliers for 16-bit image processing applications

High-Performance Carry Select Adders

High Performance Approximate Memories for Image Processing Applications

Comparison and extension of high performance adders for hybrid and error tolerant applications