M
M. Prince
Researcher at Intel
Publications - 8
Citations - 2561
M. Prince is an academic researcher from Intel. The author has contributed to research in topics: Transistor & PMOS logic. The author has an hindex of 7, co-authored 7 publications receiving 2334 citations.
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Proceedings ArticleDOI
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
Kaizad Mistry,C. Allen,C. Auth,B. Beattie,Daniel B. Bergstrom,M. Bost,M. Brazier,M. Buehler,Annalisa Cappellani,R. Chau,C. H. Choi,G. Ding,K. Fischer,Tahir Ghani,R. Grover,W. Han,D. Hanken,M. Hattendorf,J. He,J. Hicks,R. Huessner,D. Ingerly,Pulkit Jain,R. James,L. Jong,Subhash M. Joshi,C. Kenyon,K. Kuhn,K. Lee,Huichu Liu,J. Maiz,B. Mclntyre,P. Moon,J. Neirynck,S. Pae,C. Parker,D. Parsons,Chetan Prasad,L. Pipes,M. Prince,Pushkar Ranade,T. Reynolds,J. Sandford,Lucian Shifren,J. Sebastian,J. Seiple,D. Simon,Swaminathan Sivakumar,Pete Smith,C. Thomas,T. Troeger,P. Vandervoorn,S. Williams,K. Zawadzki +53 more
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Proceedings ArticleDOI
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
C. Auth,C. Allen,A. Blattner,Daniel B. Bergstrom,Mark R. Brazier,M. Bost,M. Buehler,V. Chikarmane,Tahir Ghani,Timothy E. Glassman,R. Grover,W. Han,D. Hanken,Michael L. Hattendorf,P. Hentges,R. Heussner,J. Hicks,D. Ingerly,Pulkit Jain,S. Jaloviar,Robert James,David Jones,J. Jopling,Subhash M. Joshi,C. Kenyon,Huichu Liu,R. McFadden,B. McIntyre,J. Neirynck,C. Parker,L. Pipes,Ian R. Post,S. Pradhan,M. Prince,S. Ramey,T. Reynolds,J. Roesler,J. Sandford,J. Seiple,Pete Smith,Christopher D. Thomas,D. Towner,T. Troeger,Cory E. Weber,P. Yashar,K. Zawadzki,Kaizad Mistry +46 more
TL;DR: In this paper, a 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time, which provides steep sub-threshold slopes (∼70mV/dec) and very low DIBL ( ∼50m V/V).
Proceedings ArticleDOI
A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size
Sanjay Natarajan,M. Agostinelli,S. Akbar,M. Bost,A. Bowonder,V. Chikarmane,S. Chouksey,A. Dasgupta,K. Fischer,Q. Fu,Tahir Ghani,M. Giles,S. Govindaraju,R. Grover,W. Han,D. Hanken,E. Haralson,M. Haran,M. Heckscher,R. Heussner,Pulkit Jain,R. James,R. Jhaveri,I. Jin,Hei Kam,Eric Karl,C. Kenyon,Mark Y. Liu,Y. Luo,R. Mehandru,S. Morarka,L. Neiberg,Paul A. Packan,A. Paliwal,C. Parker,P. Patel,R. Patel,C. Pelto,L. Pipes,P. Plekhanov,M. Prince,S. Rajamani,J. Sandford,Sell Bernhard,Swaminathan Sivakumar,Pete Smith,B. Song,K. Tone,T. Troeger,J. Wiedemer,M. Yang,Kevin Zhang +51 more
TL;DR: In this paper, a 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described.
Proceedings ArticleDOI
A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications
C.-H. Jan,M. Agostinelli,M. Buehler,Zhanping Chen,S.-J. Choi,G. Curello,H. Deshpande,S. Gannavaram,Hafez Walid M,U. Jalan,M. Kang,Pramod Kolar,K. Komeyli,B. Landau,A. Lake,N. Lazo,Seung Hwan Lee,T. Leo,J. Lin,Nick Lindert,S. Ma,L. McGill,C. Meining,A. Paliwal,Joodong Park,K. Phoa,Ian R. Post,N. Pradhan,M. Prince,Abdur Rahman,J. Rizk,L. Rockford,G. Sacks,A. Schmitz,H. Tashiro,Curtis Tsai,P. Vandervoorn,J. Xu,L. Yang,J.-Y. Yeh,J. Yip,Kevin Zhang,Yuegang Zhang,P. Bai +43 more
TL;DR: The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently.
Proceedings ArticleDOI
An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V
Scott E. Thompson,Mohsen Alavi,R. Arghavani,A. Brand,Robert M. Bigwood,J. Brandenburg,B. Crew,Valery M. Dubin,Makarem A. Hussein,P. Jacob,C. Kenyon,E. Lee,B. McIntyre,Z. Ma,Peter K. Moon,P. Nguyen,M. Prince,R. Schweinfurth,Swaminathan Sivakumar,Pete Smith,M. Stettler,S. Tyagi,M. Wei,J. Xu,Simon Yang,M. Bohr +25 more
TL;DR: In this paper, Tyagi et al. presented a leading edge 130 nm technology with 6 layers of Cu interconnects and 1.3 V operation, and a 5% linear shrink to reduce the 6-T SRAM cell to 2.00 µm.