M. Priyadharshni

Bio: M. Priyadharshni is an academic researcher from VIT University. The author has contributed to research in topics: Adder & Multiplication. The author has an hindex of 2, co-authored 4 publications receiving 8 citations.

Design of Imprecise Multipliers by Using Approximate Technique for Error Resilient Applications

Abstract: Approximate computing is the perfect way for error resilient applications with progress in speed and power but tradeoff with computational accuracy. In this paper, Imprecise Multipliers (IMs) are r...

A Comparative Exploration About Approximate Full Adders for Error Tolerant Applications.

Abstract: Arithmetic units such as adders and multipliers play an essential role in the performance of Digital signal processor (DSP) systems. The efficiency of the Processors are influenced by the speed and power consumption of arithmetic units. It is improved by adopting approximate computing in arithmetic units with acceptable degradation in the output. Approximate computing is an emerging topic in the past decades, it aims to achieve promising design approach with the sacrifices in computational quality for error resilient applications. Approximate computing can be adopted both in hardware level and software level of research. This paper provides an elaborative investigation about approximate computing on full adders which is explored at the hardware level. The approximation is applied to full adders either at gate level or transistor level. Further, ripple carry adder is designed for varying bit width with different degrees of approximation using these approximate Full adders. Ripple carry adder is estimated based on the structural analysis such as Area, Delay Product (ADP) and Power, Delay Product (PDP) and error matrix such as pass rate, error rate, Normalized Error Distance (NED) and Mean Error Distance (MED). The ripple carry adders are designed in Verilog HDL and stimulated in Synopsys Design Compiler (DC) using tsmc 65 nm standard cell library typical corner whereas, the error characteristics is done in MATLAB.

Logically Optimal Novel 4:2 Compressor Architectures for High-Performance Applications

Abstract: Multipliers are principal arithmetic components that play a key role in determining the performance of DSP architectures. While the efficiency of multipliers relies on optimal reduction of partial products within constraint power-delay values, this can be achieved by ‘compressors’ a precisely designed special arithmetic module. In this manuscript, authors propose low-power high-performance 4:2 compressor architectures. The presented designs perform better than the contemporary designs in terms of latency, improved power-delay and area-delay product values. The principal objective of this work is to design and develop a fast 4:2 compressor circuitry with optimal trade-off between power and area by pristine logical decomposition. All the referenced and proposed designs are simulated and synthesized in synopsys design compiler using prelayout CMOS standard cell library of TSMC 65 nm. From the synthesis results, it can be seen that the proposed model provides 12.5–29.17% reduction in area and 7–14.23% reduction in propagation delay with respect to state-of-the-art 4:2 compressor designs. In addition, to estimate the performance stability in realistic applications, 4-bit, 8-bit and 16-bit Dadda multiplier integrated with proposed compressor cells is implemented and verified. The obtained synthesis results substantiate that Dadda multiplier integrated with proposed compressor cells performs better than conventional and state-of-the-art 4:2 compressor-based variants with 4–8% reduction in propagation delay, upto 23.370% reduction in area-delay product and upto 25.62% reduction in power-delay product for 4-bit multiplication, while 6.77–16.85% reduction in propagation delay, 2.62–18.70% reduction in area-delay product and 15.30–23.20% reduction in power-delay product are achieved for 8-bit multiplication. For 16-bit multiplication it shows upto 47.05% reduction in propagation delay, upto 21.68% reduction in area-delay product and upto 24.42% reduction in power-delay product for 16-bit multiplication.

A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application

Abstract: Approximate computing is gaining grip as a computing paradigm for computer vision, data analytics, and image/signal processing applications. In the era of real-time applications, approximate computing plays a significant role. In many computers including digital signal processors (DSP) and a microprocessor, adders are the main element for the implementation of signal processing applications and digital circuit design. The major problem for addition is the propagation delay in the carry chain. As the bit length of the input operand increases, the length of the carry chain increases. To address the carry propagation problem in digital systems, the most efficient adder architectures for VLSI implementation are classified as a parallel prefix adder (PPA) structure. In this paper, a novel methodology to implement and synthesize different adders (non-speculative and speculative) for any ASIC-based system is proposed. The proposed hybrid Han-Carlson and Kogge-stone speculative adders show improved performance (low power and delay) over the state-of-the-art approximate adders. If the approximation fails, then the proposed efficient error correction technique is activated. The proposed speculative H_C adder results in a 23.79% speed improvement over the proposed K_S adder, and 23.86% of energy is saved. The proposed architectures were synthesized for an operand bit length of 16 bits. Finally, the proposed adder is validated for an error-tolerant image processing application resulting in 41.2 dB PSNR.