This article presents an overview of the essential aspects in the fabrication of silicon and some silicon/germanium nanostructures by metal-assisted chemical etching. First, the basic process and mechanism of metal-assisted chemical etching is introduced. Then, the various influences of the noble metal, the etchant, temperature, illumination, and intrinsic properties of the silicon substrate (e.g., orientation, doping type, doping level) are presented. The anisotropic and the isotropic etching behaviors of silicon under various conditions are presented. Template-based metal-assisted chemical etching methods are introduced, including templates based on nanosphere lithography, anodic aluminum oxide masks, interference lithography, and block-copolymer masks. The metal-assisted chemical etching of other semiconductors is also introduced. A brief introduction to the application of Si nanostructures obtained by metal-assisted chemical etching is given, demonstrating the promising potential applications of metal-assisted chemical etching. Finally, some open questions in the understanding of metal-assisted chemical etching are compiled.

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Metal-Assisted Chemical Etching of Silicon: A Review

We present a new analytical potential fluctuations model for the interpretation of current/voltage and capacitance/voltage measurements on spatially inhomogeneous Schottky contacts. A new evaluation schema of current and capacitance barriers permits a quantitative analysis of spatially distributed Schottky barriers. In addition, our analysis shows also that the ideality coefficient n of abrupt Schottky contacts reflects the deformation of the barrier distribution under applied bias; a general temperature dependence for the ideality n is predicted. Our model offers a solution for the so‐called T0 problem. Not only our own measurements on PtSi/Si diodes, but also previously published ideality data for Schottky diodes on Si, GaAs, and InP agree with our theory.

Barrier inhomogeneities at Schottky contacts

An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

Theoretical models of Schottky-barrier height formation are reviewed. A particular emphasis is placed on the examination of how these models agree with general physical principles. New concepts on the relationship between interface dipole and chemical bond formation are analyzed, and shown to offer a coherent explanation of a wide range of experimental data.

Recent advances in Schottky barrier concepts

The formation of the Schottky barrier height (SBH) is a complex problem because of the dependence of the SBH on the atomic structure of the metal-semiconductor (MS) interface. Existing models of the SBH are too simple to realistically treat the chemistry exhibited at MS interfaces. This article points out, through examination of available experimental and theoretical results, that a comprehensive, quantum-mechanics-based picture of SBH formation can already be constructed, although no simple equations can emerge, which are applicable for all MS interfaces. Important concepts and principles in physics and chemistry that govern the formation of the SBH are described in detail, from which the experimental and theoretical results for individual MS interfaces can be understood. Strategies used and results obtained from recent investigations to systematically modify the SBH are also examined from the perspective of the physical and chemical principles of the MS interface.

The physics and chemistry of the Schottky barrier height

Numerical simulations are presented of the potential distribution and current transport associated with metal‐semiconductor (MS) contacts in which the Schottky barrier height (SBH) varies spatially. It is shown that the current across the MS contact may be greatly influenced by the existence of SBH inhomogeneity. Numerical simulations indicate that regions of low SBH are often pinched‐off when the size of these regions is less than the average depletion width. Saddle points in the potential contours in close proximity to the low‐SBH regions, which are shown to vary with the dimension and magnitude of the inhomogeneity as well as with bias, essentially determine the electron transport across the low‐SBH regions. It is these dependences of the saddle point which give rise to various abnormal behaviors frequently observed from SBH experiments, such as ideality factors greater than unity, various temperature dependences of the ideality factor, including the T 0 anomaly, and reverse characteristics which are strongly bias‐dependent. The results of these numerical simulations are shown to support the predictions of a recently developed analytic theory of SBH inhomogeneity.

Electron transport of inhomogeneous Schottky barriers: A numerical study

We identify the physical origin of the excess capacitance at Schottky diodes without an interfacial layer, i.e., intimate Schottky contacts. Measured capacitance in excess of the space-charge capacitance is shown to be caused by the injection of minority carriers into the bulk semiconductor, rather than by the presence of interface states, as previously thought. Minority-carrier injection depends sensitively on the properties of the Ohmic back-contact.

Origin of the excess capacitance at intimate Schottky contacts.

This work presents recent results on Secondary Electron flash memory, and contrasts this approach to standard for scaled, low power mass storage applications.

Secondary Electron flash-a high performance, low power flash technology for 0.35 /spl mu/m and below

Stacked-gate memory devices have been realized which for the first time demonstrate efficient hot carrier writing for drain-source bias, V/sub DS/, down to 2.5 V. Writing is achieved by channel initiated secondary electron injection, which permits writing for qV/sub DS/ below the 3.2 eV oxide barrier. Writing times of 1 ms are achieved for floating gate voltages V/sub FG/ as low as 1.2 V, with V/sub DS/=-V/sub BS/=2.5 V, voltages which can easily be derived from a single scaled power supply, the back-gate bias generated by low-current charge pumping. No high voltage transistors are required for writing or V/sub T/ convergence. Moreover, because the devices are based on a fully scaled 0.25 /spl mu/m CMOS process, NV-memory arrays can be easily integrated with a minimum of additional process steps. Tight V/sub T/ convergence together with low voltage operation and scaling compatibility makes them ideal candidates for Giga-bit Flash.

EEPROM/flash sub 3.0 V drain-source bias hot carrier writing

Reverse short channel effect (RSCE), the paradoxical increase in threshold voltage (V/sub t/) of short channel MOSFETs, has previously been explained by diffusion broadening of a buried channel profile. We report here on RSCE in transistors which have very shallow or flat channel profiles, where such broadening cannot be the mechanism. It is shown that for several different dopings and process sequences, both RSCE and anomalous body effects can be traced back to transient enhanced diffusion (TED) of the channel profile induced by source/drain implantation. A new mechanism for RSCE is proposed, in which the surface recombination of interstitials under the gate gives rise to an impurity flux to the surface, which raises the threshold. A coupled defect/impurity diffusion model allows all short channel effects on threshold to be accurately predicted. >

M.R. Pinto

Papers

Electron transport of inhomogeneous Schottky barriers: A numerical study

Origin of the excess capacitance at intimate Schottky contacts.

Secondary Electron flash-a high performance, low power flash technology for 0.35 /spl mu/m and below

EEPROM/flash sub 3.0 V drain-source bias hot carrier writing

Explanation of reverse short channel effect by defect gradients