M.R. Shaneyfelt

Bio: M.R. Shaneyfelt is an academic researcher from Sandia National Laboratories. The author has contributed to research in topics: Leakage (electronics) & Time-dependent gate oxide breakdown. The author has an hindex of 6, co-authored 9 publications receiving 1105 citations.

Radiation Effects in MOS Oxides

Abstract: Electronic devices in space environments can contain numerous types of oxides and insulators. Ionizing radiation can induce significant charge buildup in these oxides and insulators leading to device degradation and failure. Electrons and protons in space can lead to radiation-induced total-dose effects. The two primary types of radiation-induced charge are oxide-trapped charge and interface-trap charge. These charges can cause large radiation-induced threshold voltage shifts and increases in leakage currents. Two alternate dielectrics that have been investigated for replacing silicon dioxide are hafnium oxides and reoxidized nitrided oxides (RNO). For advanced technologies, which may employ alternate dielectrics, radiation-induced voltage shifts in these insulators may be negligible. Radiation-induced charge buildup in parasitic field oxides and in SOI buried oxides can also lead to device degradation and failure. Indeed, for advanced commercial technologies, the total-dose hardness of ICs is normally dominated by radiation-induced charge buildup in either parasitic field oxides and/or SOI buried oxides. Heavy ions in space can also degrade the oxides in electronic devices through several different mechanisms including single-event gate rupture, reduction in device lifetime, and large voltage shifts in power MOSFETs.

Radiation effects in SOI technologies

Abstract: Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

Single event gate rupture in thin gate oxides

Abstract: The dependence of single event gate rupture (SEGR) critical field on oxide thickness is examined for gate oxides from 6 to 18 nm. Capacitor data are compared to SEGR data from full integrated circuits. A 1/E/sub CR/ dependence is found for critical field to rupture as a function of ion linear energy transfer (LET), consistent with earlier work for power MOSFETS with oxide thicknesses from 30 to 150 nm. More importantly, critical field to rupture increases with decreasing oxide thickness, consistent with increasing oxide breakdown field prior to heavy-ion exposure. This suggests that SEGR need not be a limiting factor as future technologies scale into the deep submicron region. However, there is a great deal of uncertainty in how voltage may scale with decreasing oxide thickness, and SEGR may continue to be a concern for devices that operate at electric fields significantly higher than 5 MV/cm.

Effects of burn-in on radiation hardness

Abstract: Transistors and ICs were irradiated with or without pre-irradiation elevated-temperature biased stresses (i.e., burn-in). These stresses lead to larger radiation-induced transistor threshold-voltage shifts and increases in IC static power supply leakage current (two orders of magnitude) in stressed ICs than for ICs not subjected to a stress. In addition, these stresses led to reduced degradation in timing parameters. The major cause of the differences is less radiation-induced interface-trap buildup for transistors subjected to an elevated-temperature biased stress. These results were observed for two distinctly different technologies and have significant implications on hardness assurance testing. One could significantly (1) overestimate degradation in timing parameters resulting in the rejection of acceptable ICs and increased system cost, or (2) underestimate the increase in static supply leakage current of ICs leading to system failure. These results suggest that radiation qualification testing must be performed on integrated circuits that have been subjected to all high-temperature biased stresses experienced in normal production flow or system use. >

Wafer-level radiation testing for hardness assurance

Abstract: To implement the qualified manufacturers list (QML) approach to hardness assurance in a practical and cost-effective manner, one must identify technology parameters that affect radiation hardness and bring them under statistical process control. To aid this effort, the authors have developed a wafer-level test system to map test-structure and IC response across a wafer. This system permits current-voltage and charge-pumping measurements on transistors, and high-frequency capacitance-voltage measurements on capacitors. For frequencies up to 50 MHz, the system provides a complete menu of functional and parametric IC tests. Wafer maps and histograms of test-structure and IC response are presented for a 1.2- mu m radiation-hardened CMOS technology to illustrate the capabilities of the wafer-level test system. Statistical and deterministic approaches to correlate test structure and IC response are discussed for this technology. >

FinFETs and Other Multi-Gate Transistors

Abstract: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

Total ionizing dose effects in MOS oxides and devices

Abstract: This paper reviews the basic physical mechanisms of the interactions of ionizing radiation with MOS oxides, including charge generation, transport, trapping and detrapping, and interface trap formation. Device and circuit effects are also discussed briefly.

Radiation Effects in MOS Oxides

Abstract: Electronic devices in space environments can contain numerous types of oxides and insulators. Ionizing radiation can induce significant charge buildup in these oxides and insulators leading to device degradation and failure. Electrons and protons in space can lead to radiation-induced total-dose effects. The two primary types of radiation-induced charge are oxide-trapped charge and interface-trap charge. These charges can cause large radiation-induced threshold voltage shifts and increases in leakage currents. Two alternate dielectrics that have been investigated for replacing silicon dioxide are hafnium oxides and reoxidized nitrided oxides (RNO). For advanced technologies, which may employ alternate dielectrics, radiation-induced voltage shifts in these insulators may be negligible. Radiation-induced charge buildup in parasitic field oxides and in SOI buried oxides can also lead to device degradation and failure. Indeed, for advanced commercial technologies, the total-dose hardness of ICs is normally dominated by radiation-induced charge buildup in either parasitic field oxides and/or SOI buried oxides. Heavy ions in space can also degrade the oxides in electronic devices through several different mechanisms including single-event gate rupture, reduction in device lifetime, and large voltage shifts in power MOSFETs.

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics

Abstract: Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high-k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum...

Total Ionizing Dose Effects in MOS and Low-Dose-Rate-Sensitive Linear-Bipolar Devices

Abstract: An overview is presented of total ionizing dose (TID) effects in MOS and bipolar devices from a historical perspective, focusing primarily on work presented at the annual IEEE Nuclear and Space Radiation Effects Conference (NSREC). From the founding of the IEEE NSREC in 1964 until ~1976, foundational work led to the discovery of TID effects in MOS devices, the characterization of basic charge transport and trapping processes in SiO2, and the development of the first generations of metal-gate radiation-hardened MOS technologies. From ~1977 until ~1985, significant progress was made in the understanding of critical defects and impurities that limit the radiation response of MOS devices. These include O vacancies in SiO2, dangling Si bonds at the Si/SiO2 interface, and hydrogen. In addition, radiation-hardened Si-gate CMOS technologies were developed. From ~1986 until ~1997, a significant focus was placed on understanding postirradiation effects in MOS devices and implementing hardness assurance test methods to qualify devices for use in space systems. Enhanced low-dose-rate sensitivity (ELDRS) was discovered and investigated in linear bipolar devices and integrated circuits. From ~1998 until the present, an increasing focus has been placed on theoretical studies enabled by rapidly advancing computational capabilities, modeling and simulation, effects in ultra-thin oxides and alternative dielectrics to SiO2, and in developing a comprehensive model of ELDRS.