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M. Renovell

Bio: M. Renovell is an academic researcher. The author has contributed to research in topics: Automatic test pattern generation & Field-programmable gate array. The author has an hindex of 11, co-authored 13 publications receiving 602 citations.

Papers
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Journal ArticleDOI
TL;DR: The authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.
Abstract: Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.

170 citations

Proceedings ArticleDOI
27 Apr 1997
TL;DR: A methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices is proposed and it is demonstrated that a set of only 3 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant.
Abstract: This paper proposes a methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices. Two different approaches with different objectives are identified: the Manufacturing Test Procedure and the User Test Procedure. The proposed method is used to generate a Manufacturing Test Procedure targeting the Interconnect Structure of RAM-based FPGA. It is demonstrated that a set of only 3 Test Configurations called the Orthogonal, the Diagonal-1 and Diagonal-2 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant. Then the test of each configuration is shown equivalent to the test of classical buses. The final proposed Manufacturing Test Procedure present a constant number of Test Configurations (3) and very short Test Sequences.

116 citations

Proceedings ArticleDOI
M. Renovell, P. Faure, Jean-Michel Portal, J. Figueras1, Yervant Zorian 
30 Oct 2001
TL;DR: It is demonstrated that the implicit-scan concept allows 'over-scan' of sequential circuits resulting in highly testable circuits and is transparent for the user as well as for the FPGA mapping tools.
Abstract: Proposes a new and original FPGA architecture with testability facilities. It is first demonstrated that classical FPGA architectures do not allow one to efficiently implement sequential circuits with a scan chain. It is consequently proposed to modify the architecture of classical FPGAs in order to create an implicit-scan chain into the FPGA itself called implicit scan FPGA (IS-FPGA). Using this new FPGA architecture, any sequential circuit implemented into the FPGA is 'implicitly scanned'. An original and optimal implementation of the proposed architecture is given with minimum area overhead and absolutely no delay impact. Additionally the technique is transparent for the user as well as for the FPGA mapping tools. Finally, it is demonstrated that the implicit-scan concept allows 'over-scan' of sequential circuits resulting in highly testable circuits.

52 citations

Proceedings ArticleDOI
18 Oct 1998
TL;DR: This paper addresses the problem of testing the LUT/RAM modules of configurable SRAM-based FPGAs using a minimum number of test configurations using the concept of non-redundant test that proposes to test in LUT mode the parts of the module not tested in RAM mode.
Abstract: This paper addresses the problem of testing the LUT/RAM modules of configurable SRAM-based FPGAs using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2/sup N/ memory cells is proposed taking into account the LUT and RAM modes. Concerning the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the march tests. We also propose a unique test configuration called 'pseudo shift register' for mxm arrays of modules. In this configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called 'shifted MATS++' is described. Concerning the LUT mode, we use the concept of non-redundant test that proposes to test in LUT mode the parts of the module not tested in RAM mode. Under this hypothesis, it is demonstrated that the test of a single module as well as the test of an mxm array of modules require only 3 test configurations. Using our solution, the test of a complete array of mxm LUT/RAM modules requires 4 test configurations independently of the size of the array and of the modules.

47 citations

Journal ArticleDOI
TL;DR: This paper addresses the problem of testing the RAM mode of the LUT/RAM modules of configurable SRAM-based Field Programmable Gate Arrays (FPGAs) using a minimum number of test configurations and proposes a unique test configuration called ‘pseudo shift register’ for an m × m array of modules.
Abstract: This paper addresses the problem of testing the RAM mode of the LUT/RAM modules of configurable SRAM-based Field Programmable Gate Arrays (FPGAs) using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes. Targeting the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the March tests. We also propose a unique test configuration called ‘pseudo shift register’ for an m × m array of modules. In the proposed configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called ‘shifted MATS++’ is described.

43 citations


Cited by
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Book
01 Jul 2006
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.

522 citations

Book
21 Jul 2006
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Abstract: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. · Most up-to-date coverage of design for testability. · Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. · Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. · Lecture slides and exercise solutions for all chapters are now available. · Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website. Table of Contents Chapter 1 - Introduction Chapter 2 - Design for Testability Chapter 3 - Logic and Fault Simulation Chapter 4 - Test Generation Chapter 5 - Logic Built-In Self-Test Chapter 6 - Test Compression Chapter 7 - Logic Diagnosis Chapter 8 - Memory Testing and Built-In Self-Test Chapter 9 - Memory Diagnosis and Built-In Self-Repair Chapter 10 - Boundary Scan and Core-Based Testing Chapter 11 - Analog and Mixed-Signal Testing Chapter 12 - Test Technology Trends in the Nanometer Age

340 citations

Patent
Sheng Feng1, Jung-Cheun Lien1, Eddy C. Huang1, Chung-yuan Sun1, Tong Liu1, Naihui Liao1, Weidong Xiong1 
31 Jan 2002
TL;DR: In this paper, a plurality of FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals.
Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

210 citations

Proceedings ArticleDOI
18 Oct 1998
TL;DR: The first BIST approach for testing the programmable routing network in FPGAs is introduced, which detects opens in, and shorts among, wiring segments, and also faults affecting theprogrammable switches that configure the FPGA interconnect.
Abstract: We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affecting the programmable switches that configure the FPGA interconnect. As a result, the BIST technique provides complete testing of interconnect faults.

180 citations

Journal ArticleDOI
TL;DR: The authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.
Abstract: Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.

170 citations