M. Renovell

Bio: M. Renovell is an academic researcher. The author has contributed to research in topics: Automatic test pattern generation & Field-programmable gate array. The author has an hindex of 11, co-authored 13 publications receiving 602 citations.

TOF: a tool for test pattern generation optimization of an FPGA application oriented test

Abstract: The objective of this paper is to generate an Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault." Then, it is commented that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is also commented that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.

A Specific Test Methodology for Symmetric SRAM-Based FPGAs

Abstract: This paper describes a test methodology for symmetric SRAM-based FPGAs. From a fundamental point of view, a test methodology for FPGAs differs from the test methodology for ASICs mainly due to the configurability of such flexible devices. In the paper, the FPGA architecture is first analyzed identifying the test problems specific to FPGAs as well as the test properties. This architecture is divided into different architectural elements such as the logic cells, the interconnect cells and the RAM cells. For each architectural element appropriated fault models are proposed, and test configurations and test vectors are derived targeting the proposed fault models.

SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules

Abstract: The configurable logic cells of the SRAM-based FPGA are mainly described as an interconnection of functional logic module. In this paper, we state that the stuck-at fault model can be used on such a description when multiplexer-based module are under consideration. To validate this assumption, the following step are realized. A test sequence is generated for the functional description assuming a stuck-at fault model of the input/output. The test sequence is applied, on a logic gate implementation assuming a stuck-at fault model of the gates nodes and then, on a transmission gate implementation assuming a short fault model. In the both case the fault coverage is 100%.

VLSI Test Principles and Architectures: Design for Testability

Abstract: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. · Most up-to-date coverage of design for testability. · Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. · Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. · Lecture slides and exercise solutions for all chapters are now available. · Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website. Table of Contents Chapter 1 - Introduction Chapter 2 - Design for Testability Chapter 3 - Logic and Fault Simulation Chapter 4 - Test Generation Chapter 5 - Logic Built-In Self-Test Chapter 6 - Test Compression Chapter 7 - Logic Diagnosis Chapter 8 - Memory Testing and Built-In Self-Test Chapter 9 - Memory Diagnosis and Built-In Self-Repair Chapter 10 - Boundary Scan and Core-Based Testing Chapter 11 - Analog and Mixed-Signal Testing Chapter 12 - Test Technology Trends in the Nanometer Age

Tileable field-programmable gate array architecture

Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Built-in self-test of FPGA interconnect

Abstract: We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affecting the programmable switches that configure the FPGA interconnect. As a result, the BIST technique provides complete testing of interconnect faults.

Testing the interconnect of RAM-based FPGAs

Abstract: Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.