The temporal read noise on the signal path of a complementary metal-oxide semiconductor image sensor is analyzed to investigate the effectiveness of high-gain column amplifiers in enhancing sensor sensitivity. The signal path examined includes a pixel source follower, a switched-capacitor, noise-cancelling, high-gain amplifier, and a sample-and-hold circuit in each column. It is revealed that the total random readout noise consists of a component due to noise charge sampled and held at the charge summation node of the amplifier and transferred to the output, and a direct noise component sampled at the sample-and-hold stage at the output of the column amplifier. The analysis suggests that the direct noise components can be greatly reduced by increasing the column amplifier gain, indicating that an extremely low-noise readout circuit may be achievable through the development of a double-stage noise-cancelling architecture.

Noise analysis of high-gain, low-noise column readout circuits for CMOS image sensors

A high-sensitivity CMOS image sensor using gain-adaptive column amplifiers is presented and tested. The use of high gain for the column amplifier reduces input-referred random noise, and when coupled with a column-based digital noise cancellation technique, also reduces fixed pattern noise. An experimental application of the circuit using 0.25-/spl mu/m CMOS technology with pinned photodiodes gave an rms random noise of 263 /spl mu/V and an rms fixed pattern noise of 50 /spl mu/V.

A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects In the CMS, the gain of the noise cancelling is controlled by the number of samplings It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises Two types of the CMS with simple integration and folding integration are proposed In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor Using 16 samplings, dynamic range of 594 dB and noise level of 19 e(-) for the simple integration CMS and 75 dB and 22 e(-) for the folding integration CMS, respectively, are obtained

https://www.mdpi.com/1424-8220/10/10/9139/pdf

Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects.

A 3.9-/spl mu/m pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel has been developed for mobile applications. The newly developed CMOS pixel architecture realizes the minimum number of the transistors in one pixel. Small pixel size and sufficient fill factor are achieved by using the shared pixel architecture and floating diffusion driving. High conversion gain, low random noise, and low dark current are achieved by buried photodiode with complete charge transfer capability and correlated double sampling (CDS) circuit. The image sensor is fabricated in a thin planarized 0.35-/spl mu/m single poly-Si double-metal customized CMOS process in order to provide good image performance. The image sensor achieves low noise floor of 330 /spl mu/V and low dark current of 50 pA/cm/sup 2/ at 45/spl deg/C. This image sensor also realized various functions by on-chip digital and analog circuits.

A 3.9-/spl mu/m pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel

A 2.5V CMOS image sensor using a pixel configuration of four photodiodes in one unit sharing seven transistors is presented. This image achieves a 2.25/spl mu/m pixel pitch with 25% aperture ratio in a 0.25/spl mu/m IP2M CMOS process.

A 1/4in 2M pixel CMOS image sensor with 1.75 transistor/pixel

A 0.25 /spl mu/m technology CMOS image sensor employs a 4.2 /spl mu/m pitch pinned-photodiode pixel. A column amplifier and digital domain processing reduce the fixed pattern noise to 55 /spl mu/V. The saturation voltage is 1 V with a 2.5 V supply voltage, and the dynamic range is 69 dB.

M. Sakakibara

Papers

A column-based pixel-gain-adaptive CMOS image sensor for low-light-level imaging