M. Santosh

Bio: M. Santosh is an academic researcher from Academy of Scientific and Innovative Research. The author has contributed to research in topics: CMOS & Neuromorphic engineering. The author has an hindex of 1, co-authored 4 publications receiving 3 citations.

Silicon Nanowire Based Platform Device for Chemical/Bio-Chemical Sensing Applications

Abstract: Silicon nanowire (SiNW) arrays are fabricated using complementary metal-oxide semiconductor (CMOS) compatible technology, for the detection of proteins, pH levels, cardiac biomarker troponin-T (cTnT) etc. The sensor output is fed to a ‘current to frequency converter circuit’. Neuromorphic approach based low input referred noise frequency converter circuit is developed. The circuit generates a sequence of spikes with the help of Leaky integrate and fire neuron model (LIF) where firing delay maps to the strength of the stimulation across the array. The proposed read-out circuit is implemented using Tower Jazz Semiconductor's 0.18μm CMOS technology. The SiNW arrays are producing current change from 200pA to 1.6nA for a corresponding change of 50m V/0.5ng/ml protein concentration at the gate. The circuit is able to detect a change in current as low as 50pA and consuming IlμW power and 93×17μm2silicon area.

Neuromorphic Approach based Current Sensing Analog to Digital Converter for Biomedical Applications

Abstract: A current sensing analog-to-digital converter (CADC) targeting biomedical applications is proposed in this paper. The proposed architecture consists of a leaky integrate and fire (LIF) neuron model inspired from neuromorphic circuits along with digital control circuits and error correction circuit to enhance INL/DNL performance. The architecture is tuned for input signal ranging from 1 µA to 64 µA with power supply of 1/1.8 V for digital and analog blocks respectively. The design is implemented in 0.18 µm CMOS 1P4M triple-well process of Tower Jazz Semiconductor's technology. Total power consumption of the circuit is 1. 95 mW & 48.86 μW respectively and achieves FoM of 331.6 & 71.24 pJ/conversion-step for the cases with and without error correction for 6-bits operation.

Emulation of MEMS Capacitive Sensor for CMOS Interface Circuit Validation

Abstract: A MEMS capacitive sensor is emulated on a PCB for quick validation of CMOS interface circuit In capacitive sensor, capacitance changes with external force; to mimic similar changes, controlled magnetic field is applied on emulated PCB capacitor The dimension optimizations of interdigital capacitor are performed using CST software The simulated values are milled on a FR4 sheet to make PCB capacitor The simulated capacitance values are cross checked by making measurement using LCR meter on PCB capacitor and have a deviation of 65% The complete MEMS emulator consists of PCB capacitor, permanent magnet controlled by screw gauge and gauss meter A minimum change of 50 aF achieved over a base capacitance 19 pF

Reconfigurable Digital Logic Gate Based on Neuromorphic Approach

Abstract: This paper presents low power and highly tuneable LIF (modified) neuron model and its usage to implement reconfigurable digital logic gate. Simulations are done using Tower Jazz Semiconductor's 180nm technology and UMC 28 nm technology in Cadence virtuoso environment. Results show the advantage of neuromorphic approach in terms of re-configurability, power and area when compared to traditional logic gate designs. Reconfigurable gate performs AND/OR/NAND/NOR/XOR/XNOR. It works for both spiking input as well as DC input (current signal). Power consumption of reconfigurable gate designed using modified LIF is at least 45% less than the power consumption of CMOS gates.

Neuromorphic Approach based Current Sensing Analog to Digital Converter for Biomedical Applications

Abstract: A current sensing analog-to-digital converter (CADC) targeting biomedical applications is proposed in this paper. The proposed architecture consists of a leaky integrate and fire (LIF) neuron model inspired from neuromorphic circuits along with digital control circuits and error correction circuit to enhance INL/DNL performance. The architecture is tuned for input signal ranging from 1 µA to 64 µA with power supply of 1/1.8 V for digital and analog blocks respectively. The design is implemented in 0.18 µm CMOS 1P4M triple-well process of Tower Jazz Semiconductor's technology. Total power consumption of the circuit is 1. 95 mW & 48.86 μW respectively and achieves FoM of 331.6 & 71.24 pJ/conversion-step for the cases with and without error correction for 6-bits operation.

On-Chip Adaptive Implementation of Neuromorphic Spiking Sensory Systems with Self-X Capabilities

Abstract: In contemporary devices, the number and diversity of sensors is increasing, thus, requiring both efficient and robust interfacing to the sensors. Implementing the interfacing systems in advanced integration technologies faces numerous issues due to manufacturing deviations, signal swings, noise, etc. The interface sensor designers escape to the time domain and digital design techniques to handle these challenges. Biology gives examples of efficient machines that have vastly outperformed conventional technology. This work pursues a neuromorphic spiking sensory system design with the same efficient style as biology. Our chip, that comprises the essential elements of the adaptive neuromorphic spiking sensory system, such as the neuron, synapse, adaptive coincidence detection (ACD), and self-adaptive spike-to-rank coding (SA-SRC), was manufactured in XFAB CMOS 0.35 μm technology via EUROPRACTICE. The main emphasis of this paper is to present the measurement outcomes of the SA-SRC on-chip, evaluating the efficacy of its adaptation scheme, and assessing its capability to produce spike orders that correspond to the temporal difference between the two spikes received at its inputs. The SA-SRC plays a crucial role in performing the primary function of the adaptive neuromorphic spiking sensory system. The measurement results of the chip confirm the simulation results of our previous work.