This Paper presents high Speed pipeline 64-point FFT processor based on Radix-22 for wireless LAN communication systems. This method uses Radix-2 butterfly structure and Radix-22 CFA algorithm. Radix-2 butterfly's complexity is very low and Radix-22 CFA algorithm reduces number of twiddle factors compared to Radix-4 and Radix-2. An efficient VHDL code has been written, synthesized successfully using XST of Xilinx ISE 14.1 and simulated using ModelSim PE Student Edition 10.4a. Also MATLAB code has been written and simulated with MATLAB R2012a tool. The computation speed of proposed design is observed to be 158.96 MHz after the synthesis process and SQNR 37.02dB for 64 point.

High speed pipelined 64-point FFT processor based on Radix-2 2 for wireless LAN

This paper proposes fast performance reconfigurable pipeline variable points FFT processor design. This design is proposed for variable N points whose values can be 8, 16, 32, 64, 128, 256 and 512 sample points. Hence, the proposed reconfigurable design can be used for different points OFDM applications rather using different designs. The proposed implementation design uses Radix-2 Common Factor Algorithm (CFA) algorithm and SDF architecture. Radix-2 CFA algorithm reduces the number of twiddle factors compared to Radix-4 and Radix-2 and utilizes Radix-2 butterfly structure whose complexity is very low. SDF architecture uses less memory and utilizes multipliers fully compared to others. The frequency of proposed design is varied with the FFT points N. The proposed design is synthesized successfully using XST of Xilinx ISE 14.1 and simulated using ModelSim & MATLAB tool to verify results. Synthesized results of the proposed design for 512 points are 155.9 MHz max frequency, slice used 1795, slices Flip Flops used 1028 and LUTs used 3335 which are approximately 37% higher, 35%, 19%, 27% lesser in ratio than convention FFTs. 

/pdf/fast-performance-pipeline-re-configurable-fft-processor-1jvyrs2jmu.pdf

Fast Performance Pipeline Re-Configurable FFT Processor Based on Radix-22 for Variable Length N

This paper focus on the study of an efficient Radix-4 FFT and CORDIC algorithm. Due to use of Radix-4 speed gets doubled than Radix-2 in FFT computation. For twiddle factor calculation Co-ordinate Rotation Digital Computer (CORDIC) algorithm is used, which will reduce the computation time and make processor faster. The CORDIC offers the opportunity to calculate all the required functions in a rather simple and elegant fashion. In the next phase of this paper, actual Implementation of FFT processor on FPGA will be done using VHDL.

/pdf/study-of-radix-4-fft-processor-using-cordic-l76rexthki.pdf

Study of Radix-4 FFT Processor using CORDIC

The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal, image processing and FFT processor is a critical block in all multi- carrier systems used primarily in the mobile environment. Fast Fourier transform (FFT) is an efficient implementation of the discrete Fourier transform (DFT). The portability requirement of these systems is mainly responsible for the need of low power FFT architectures. . In this study, the development of 64 point FFT, based on Decimation-In- Time (DIT) domain using Radix-4 algorithm. The complex multiplier is one of the most power consuming blocks in the FFT processor. A significant property of the proposed method is that the critical path of the address generator is independent from the FFT transform length N, making it extremely efficient for large FFT transforms. The results confirm the speed and area advantages for large FFTs. Although only radix-4 FFT address generation is presented in the paper, it can be used for higher radix FFT.

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Papers

Design and simulation of 64 point FFT using Radix 4 algorithm for FPGA Implementation