M. Vanitha

Bio: M. Vanitha is an academic researcher from VIT University. The author has contributed to research in topics: Very-large-scale integration & Field-programmable gate array. The author has an hindex of 3, co-authored 4 publications receiving 16 citations.

Highly secured high throughput VLSI architecture for AES algorithm

Abstract: This paper provides an efficient VLSI architecture to increase the throughput and security of the Advanced Encryption Standard (AES) Algorithm. The existing architecture provide the Look up Table technique for the Subbytes and inverse Subbytes transformation used in AES algorithm, our proposed technique uses combinational circuit and pipelining technique which increase the throughput and reduce the delay. This design proposes a new technique for implementing the S-box, which decides the speed and power of AES architecture and the basic components of this architecture is made completely fault detectable by using pseudo-nMOS technology and thereby increases the security of this system. This AES design was modeled using Verilog HDL and synthesized using TSMC's 90 nm standard cell library with RTL Compiler, and physical design implementation was done using SOC Encounter and thereby achieved a through put of 58.18 Gbps after detailed routing. The basic security of the system is validated by using Cadence Virtuoso in the transistor level design.

Low power high throughput reconfigurable stream cipher hardware VLSI architectures

Abstract: This work reports power efficient high throughput VLSI hardware architecture for RC4 stream cipher. Two VLSI architectures have been developed for RC4 algorithm which shows power efficiency and frequency/throughput improvement compared to the existing FPGA implementations. Naturally, the ASIC implementation of the same shows more power and PDP reduction compared with existing FPGA architectures. The first architecture Proposed-I S-box developed by replacing the RAM based S-box, with combinational circuits providing a means for reducing the critical path. Pipelining applied in the S-box increases the speed and reduces the power consumed. Second architecture Proposed-II LFSR has been developed using LFSR and FSM based control for key scheduling algorithm. These architectures were first implemented by targeting for FPGA and the same designs were targeted for an ASIC chip. Finally, a novel VLSI architecture has been proposed with an intention of sharing the S-box resources for RC4 and AES algorithm expectedly saving area and power.

Modified Low Power Dynamic Adder for High Performance

Abstract: This paper proposes a modified form of the design for low dynamic power adder using a reset network in the CMOS dynamic logic family. The results show that the dynamic power reduces as compared to lower dynamic power logic and the domino logic. In this modified form of the low dynamic power adder, the logic outputs are reset to low during the pre-discharge phase which is the high input to the clock. The logic evaluation takes place when the clock input is low. The modified logic is better than domino logic since it does not require an inverter for cascading the gates. In Pre-discharging, resetting the output low prevents the problems of charge sharing and charge leakage associated with the other dynamic logic families and also it avoids the static power dissipation which exists in the low power dynamic logic. Also resetting the output low avoids the problem of high transition time from high level to low level which exists in circuits employing PMOS logic. The proposed circuit is a mix of PMOS logic and a dynamic logic. The proposed logic cell can be cascaded in a domino like fashion without the need of an inverter.

Low-Power Area Efficient Reconfigurable Pipelined Two’s Complement Multiplier with Reduced Error

Abstract: This paper describes reconfigurable two’s complement multiplier using Baugh Wooley’s algorithm supporting six modes of operation. A fixed width Baugh Wooley multiplier is used as prototype for the architecture. Error reduction technique based on bias compensation vector is introduced in the design to achieve a low error fixed width product. Clock gating technique and zero input method is used to obtain a power efficient design. A power reduction of 8.14% and 7.39% is achieved for the current design compared to other non-reconfigurable and reconfigurable techniques. Also a higher clock frequency of 200 MHz is supported by the current architecture compared to other reconfigurable structure which supports 100 MHz for the same reconfigurable two’s complement multiplication. Area of the proposed power efficient architecture is also reduced by 32.64% compared to the previous reconfigurable architecture.

Optimization and Implementation of AES Algorithm Based on FPGA

Abstract: This paper presented an optimizing AES algorithm implementation to get smaller area and higher throughput. The main contributions of the optimization part are as follows. Initially, this paper combined multiple steps of round units into a set of more complete lookup tables to achieve parallel lookup and to obtain increased speed of the process of round units. Additionally, a dual port ROM structure was used to implement lookup tables to improve the utilization of FPGA storage units. Lastly, a fully unrolled three-stage inner and outer double pipelined architecture was used to improve data throughput. ISE software was used to carry out synthesis and timing analysis for AES algorithm module designed by this paper on Virtex-6 platform. The results showed that the area and efficiency of the AES algorithm implementation by using the optimizing design had obvious advantages over the related references. The maximum frequency and throughout of the design can be improved, which is about 470.998MHz and 60.29Gbps with small area implementation. The efficiency is increased to 26.77.

Energy aware load balancing for computational cloud

Abstract: Cloud computing is novel technology, which enables any resource as service on demand. Cloud environment motivates highly dynamic resource provisioning. Hence clients can scale up or scale down their requirements as per their demand. Load balancing is very important and complex problem in cloud environment, because of its heterogeneity of the computing nodes. In order to realize the full potential of cloud computing it is vital to minimize energy consumption along with effective load balancing. The aim of Energy Aware Load Balancing (EALB) model is to minimize energy consumption with load balancing. EALB model classifies the incoming job request either CPU bound or I/O bound according to their purpose and behaviour. This classification details are maintained in a table named Pattern History Table (PHT) and organized as hash table. One of the virtual machine (VM) is selected dynamically based on best fit allocation policy and the job is assigned to the victimized VM. From the pattern history table job's nature is identified. Using Dynamic Voltage Frequency Scaling (DVFS) scheme the selected VM's processor clock frequency is increased if it is found CPU bound else decreased (I/O bound). Thus, EALB algorithm saves considerable amount of energy and proves to be more efficient.

Study of Data Security Algorithms using Verilog HDL

Abstract: This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using ModelSim.

A high performance, race eliminated, two phase nonoverlapping clocked All-N-Logic for both strong and subthreshold designs

Abstract: In this paper, a new structure of ANL logic, named TPANL, is presented to achieve higher performance, lower power consumption and eliminating glitches. Different ANL logics suffer from output glitches due to race problem. Our proposed TPANL logic by two phase nonoverlapping clocks eliminates output glitches and reduces glitch power. TPANL logic speedup is mainly due to reduced capacitance at each evaluation node of a dynamic circuit. This logic works in both operational region of strong inversion and subthreshold region, with 10GHz to 12.5MHz respectively. In spite of NonInv./Inv. pipeline in ANL logics, TPANL is based on NonInv./NonInv. pipeline and therefore it solves the voltage drops on NMOS Inv. stages in subthreshold regions. The simulation results of 4-bit CLA adder show 27% and 72.9% power consumption reduction, also, 60% and 50% performance improvement, in strong inversion region rather than ANL and DPANL respectively. The 4-bit CLA adder with TPANL logic in the subthreshold region has about 92nW power consumption.