Modeling of SOI four-gate transistor (G4FET) using multidimensional spline interpolation method

Circuit simulation is an indispensable part of modern IC design. The significant cost of fabrication has driven researchers to verify the chip functionality through simulation before submitting the design for final fabrication. With the impending end of Moore’s Law, researchers all over the world are looking for new devices with enhanced functionality. A plethora of promising emerging devices has been proposed in recent years. In order to leverage the full potential of such devices, circuit designers need fast, reliable models for SPICE simulation to explore different applications. Most of these new devices have complex underlying physical mechanism rendering the model development an extremely challenging task. For the models to be of practical use, they have to enable fast and accurate simulation that rules out the possibility of numerically solving a system of partial differential equations to arrive at a solution. In this chapter, we show how different modeling approaches can be used to simulate three emerging semiconductor devices namely, silicononinsulator four gate transistor(GFET), perimeter gated single photon avalanche diode (PG-SPAD) and insulator-metal transistor (IMT) device with volatile memristance. All the models have been verified against experimental /TCAD data and implemented in commercial circuit simulator.

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Modeling Emerging Semiconductor Devices for Circuit Simulation

Wave function penetration has significant impact on nanoscale devices having ultrathin gate oxide. Although wave function penetration effects on ballistic drain current and capacitance-voltage characteristics in nanoscale devices have been reported in literature, to the best of the authors’ knowledge, effects of temperature on drain current incorporating with and without wave function penetration are yet to be studied. In this work, the impacts of temperature, gate dielectric and film thickness in wave function penetration on ballistic drain current of nanoscale double-gate (DG) MOSFETs are presented. The effects are observed using two-dimensional self-consistent solution of Schrodinger and Poisson equations. It has been obtained that temperature effect on drain current is greatly dependent on silicon surface orientation. Drain current of DG MOSFETs fabricated on $$\langle110\rangle$$
 surface is more sensitive to temperature compared to $$\langle001\rangle$$
 surface. This has been obtained for both the cases with and without incorporating wave function penetration in silicon–gate oxide interface. Electrostatics behind this phenomenon has been explained from the transmission probability of electrons from source to drain which is largely influenced by temperature on $$\langle110\rangle$$
 surface compared to $$\langle001\rangle.$$
 Moreover, the transmission coefficient is significantly affected by wave function penetration in $$\langle110\rangle \hbox{ than }\langle001\rangle$$
 surface. Both these demonstrate greater sensitivity of temperature and wave function penetration in $$\langle110\rangle$$
 silicon surface orientation compared to $$\langle001\rangle.$$
 Furthermore, gate dielectric with lower conduction band offset and device scaling with thin channel thickness tend to exhibit greater impact of wave function penetration.

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Analysis of temperature and wave function penetration effects in nanoscale double-gate MOSFETs

In this paper, the effect of gate bias using potential distribution for Graphene channel Four Gate Transistor (G4-FET) and Gate-All-Around (GAA) MOSFET have been shown. Potential distribution is obtained by solving 2-D Poisson equation using COMSOL with MATLAB. The potential profile for G4-FET and GAA MOSFET have also been compared.

Effect of Gate Bias on Graphene Channel of G 4 -FET and Gate-All-Around MOSFET

One major concern of channel engineering in nanotransistors is the coupling of the conduction channel to the source/drain contacts. In a number of previous publications, we have developed a semiempirical quantum model in quantitative agreement with three series of experimental transistors. On the basis of this model, an overlap parameter 0 ≤ C ≤ 1 can be defined as a criterion for the quality of the contact-to-channel coupling: A high level of C means good matching between the wave functions in the source/drain and in the conduction channel associated with a low contact-to-channel reflection. We show that a high level of C leads to a high saturation current in the ON-state and a large slope of the transfer characteristic in the OFF-state. Furthermore, relevant for future device miniaturization, we analyze the contribution of the tunneling current to the total drain current. It is seen for a device with a gate length of 26 nm that for all gate voltages, the share of the tunneling current becomes small for small drain voltages. With increasing drain voltage, the contribution of the tunneling current grows considerably showing Fowler–Nordheim oscillations. In the ON-state, the classically allowed current remains dominant for large drain voltages. In the OFF-state, the tunneling current becomes dominant.

Channel Engineering for Nanotransistors in a Semiempirical Quantum Transport Model

A charge sheet model is proposed to analyze the transistor characteristics of fully depleted SOI four gate field effect transistors (G 4 -FETs). The model is derived assuming a parabolic potential variation between the junction-gates and by solving 2-D Poisson’s equation. The proposed model facilitates the calculation of surface potential and charge densities as a function of all gate biases. Modifying this charge sheet model for non-equilibrium condition, current–voltage and capacitance–voltage characteristics are also analyzed. Different back surface charge conditions are considered for each analysis. The models are compared with 3-D Silvaco/Atlas simulation results which show good agreement.

Analytical modeling of surface accumulation behavior of fully depleted SOI four gate transistors (G4-FETs)

A mathematical model is developed to determine the 3-D potential distribution of a fully-depleted silicon-on-insulator (SOI) four-gate transistor (G4-FET). The potential distributions along the channel and between the junction-gates are assumed to be parabolic due to short channel effect. Using these two assumptions, the 3-D potential distribution model is developed. From the 3-D model, expression for threshold voltage is derived considering all possible charge conditions at the back surface. The proposed models successfully correlate the effect of all four gates and consider the impact of channel length, drain voltage and other device dimensions.

Three dimensional modeling of SOI four gate transistors

An analytical model is developed to determine the 3-D potential distribution of a fully-depleted silicon-on-insulator (SOI) four-gate transistor (G4-FET) The potential variations along the channel and between the junction-gates are assumed to be parabolic due to short channel effect and presence of MOS gates Using these assumptions and with necessary boundary conditions, the 3-D Poisson's equation is solved to formulate the overall expression The proposed model successfully correlates the four gates of the device and shows excellent agreement with the charge variation along the channel Slight modification also agrees with the surface potential of a DGFET

Analytical expression of the three-dimensional potential distribution of a SOI four-gate transistor

Analytical modelling of Early Voltage (V A ) and Common Emitter Current Gain (β) of Heterojunction Bipolar Transistor (HBT) are derived considering field dependent mobility, doping dependent mobility, Band Gap Narrowing (BGN), changes in density of state (DOS) and velocity saturation effect. BGN was considered due to heavy doping and presence of Germanium. The effect of various base doping profiles (Gaussian, exponential and uniform) and germanium profile (trapezoidal/triangular/box) on V A and β are addressed. The results of the analysis are compared with the data available in the previous research work.

M. Ziaur Rahman Khan

Papers

Analytical modeling of surface accumulation behavior of fully depleted SOI four gate transistors (G4-FETs)

Three dimensional modeling of SOI four gate transistors

Analytical expression of the three-dimensional potential distribution of a SOI four-gate transistor

Analysis of temperature and wave function penetration effects in nanoscale double-gate MOSFETs

Analytical modelling of Early voltage and Current Gain of Si 1−y Ge y Heterojunction Bipolar Transistor