Madhava Sarma Vemuri

Bio: Madhava Sarma Vemuri is an academic researcher from North Dakota State University. The author has contributed to research in topics: Integrated circuit & Inductor. The author has an hindex of 1, co-authored 5 publications receiving 2 citations.

Recent advances in dielectrophoresis toward biomarker detection: A summary of studies published between 2014 and 2021.

Abstract: Dielectrophoresis is a well-understood phenomenon that has been widely utilized in biomedical applications. Recent advancements in miniaturization have contributed to the development of dielectrophoretic-based devices for a wide variety of biomedical applications. In particular, the integration of dielectrophoresis with microfluidics, fluorescence, and electrical impedance has produced devices and techniques that are attractive for screening and diagnosing diseases. This review article summarizes the recent utility of dielectrophoresis in assays of biomarker detection. Common screening and diagnostic biomarkers, such as cellular, protein, and nucleic acid, are discussed. Finally, the potential use of recent developments in machine learning approaches toward improving biomarker detection performance is discussed. This review article will be useful for researchers interested in the recent utility of dielectrophoresis in the detection of biomarkers and for those developing new devices to address current gaps in dielectrophoretic biomarker detection.

Dual-Purpose Metal Inter-layer Via Utilization in Monolithic Three-Dimensional (M3D) Integration

Abstract: Monolithic three-dimensional integrated circuit (M3D-IC) technology can potentially improve transistor density, performance and power efficiency for future IC designs. To attain maximum benefits of M3D-IC technology, the silicon footprint overhead caused by metal inter-layer via (MIV) should be reduced because MIV passes through the silicon. In this paper, we present dual-purpose MIV utilization where MIV serves two purposes: 1. interconnect and 2. device terminal. The active devices that are formed by using MIV such as MIV-based capacitor and MIV-based transistor are studied in detail. We demonstrate the advantage of these dual-purpose MIV-based device utilization in on-chip circuits by implementing an inverter. Simulation results suggest that the inverter designed with our approach occupies 13844 nm2 silicon area. The silicon area utilization of the inverter is reduced by up to 24% compared with the conventional transistor-level implementation of inverter in M3D-IC process by utilizing MIV-based transistor.

Design and Optimization of Magnetic-core Solenoid Inductor for Multi-phase Buck Converter

Abstract: Due to heterogeneous integration, there is an increased demand for on-chip voltage regulators to provide many voltage domains for efficient operation of the system. Towards this, planar magnetic-core based inductors gained popularity due to their increased inductance density for on-chip buck converter realization. To ensure proper operation of the converter, the magnetic-core should not saturate, and over-design of the inductor decreases the efficiency of the converter significantly. Also, the magnetic-core area budget allocated to the converter implementation will be limited. This paper details the design and analysis of magnetic-core solenoid inductor based multi-phase buck converter. Also, an optimization framework to design an efficient multi-phase buck converter for the given specifications with the magnetic-core solenoid inductor is proposed. Full-wave simulations on commercial tool show that the multi-phase buck converter designed with our optimization framework achieves 92.8% efficiency and 0.5mV voltage ripple for the load current of 500 mA with the solenoid inductor is implemented with 0.397 mm2 magnetic-core area for the given specifications.

Efficient Metal Inter-Layer Via Utilization Strategies for Three-dimensional Integrated Circuits

Abstract: Three-dimensional integrated circuit (3D-IC) technology gained prominence for future integrated chips (ICs) due to increased transistor density at the same technology node. Conventional 3D-IC implementation involves die stacking with vertical interconnects realized by through-silicon-via (TSV). One of the main challenges associated with 3D-IC technology is the TSV size since they are large in size (100-400x larger than standard cells in 45nm technology) and their diameters do not scale with technology. In addition, lot of dummy TSVs are inserted to satisfy minimum density rule laid by foundries which further increases the overhead. Also, a need for small form factor implementation of on-chip devices especially inductors are required for heterogeneous integration. In this paper, we discuss about utilizing TSVs to form on-chip inductors for various applications. On the other hand, monolithic Three-dimensional integrated circuit (M3D-IC) technology is enabled by sequential integration of substrate layers and the devices at different layers are connected by metal inter-layer via (MIV) where MIV passes through the silicon but the size very small compared with the TSV in 3D-ICs. The effective area occupied by MIV on the substrate will increase with the number of MIVs. Therefore, in this paper, we will discuss efficient strategies to reduce silicon footprint overhead by MIV through reconfiguration of silicon around MIV to design MIV-capacitor and MIV-transistor devices. TCAD simulations of 14nm channel length demonstrate that the proposed approach will reduce the silicon area of inverter by about 24% compared with the conventional approach for transistor-level M3D-IC technology.

An Improved Quadrature Voltage-Controlled Oscillator with Through-Silicon-Via Inductor in Three-dimensional Integrated Circuits.

Abstract: Low-power quadrature voltage-controlled oscillator (QVCO) design utilizing transformer-feedback and current-reuse techniques with increased frequency range is proposed in this paper. With increasing demand for QVCOs in on-chip applications, the conventional spiral inductor based approaches for QVCOs has become a major bottleneck due to their large size. To address this concern, we propose to replace the conventional spiral inductor based approaches with through-silicon-via (TSV) inductor based approach in three-dimensional integrated circuits (3D ICs). In addition, the proposed QVCO circuit can provide higher frequency range of operation compared with conventional designs. Experimental results show by replacing conventional spiral transformers with TSV transformers, up to 3.9x reduction in metal resource consumption. The proposed QVCOs achieves a phase noise of -114 $dBc/Hz$@1 $MHz$ and -111.2 $dBc/Hz$@1 $MHz$ at the carrier of 2.5 $GHz$ for toroidal TSV transformed based-QVCO and vertical spiral transformer based-QVCO respectively. The power consumption is only 1.5 $mW$ and 1.7 $mW$ for toroidal TSV transformed based-QVCO and vertical spiral transformer based-QVCO respectively, under the supply voltage of 0.7 $V$.

Label-free microfluidic cell sorting and detection for rapid blood analysis.

Abstract: Blood tests are considered as standard clinical procedures to screen for markers of diseases and health conditions. However, the complex cellular background (>99.9% RBCs) and biomolecular composition often pose significant technical challenges for accurate blood analysis. An emerging approach for point-of-care blood diagnostics is utilizing "label-free" microfluidic technologies that rely on intrinsic cell properties for blood fractionation and disease detection without any antibody binding. A growing body of clinical evidence has also reported that cellular dysfunction and their biophysical phenotypes are complementary to standard hematoanalyzer analysis (complete blood count) and can provide a more comprehensive health profiling. In this review, we will summarize recent advances in microfluidic label-free separation of different blood cell components including circulating tumor cells, leukocytes, platelets and nanoscale extracellular vesicles. Label-free single cell analysis of intrinsic cell morphology, spectrochemical properties, dielectric parameters and biophysical characteristics as novel blood-based biomarkers will also be presented. Next, we will highlight research efforts that combine label-free microfluidics with machine learning approaches to enhance detection sensitivity and specificity in clinical studies, as well as innovative microfluidic solutions which are capable of fully integrated and label-free blood cell sorting and analysis. Lastly, we will envisage the current challenges and future outlook of label-free microfluidics platforms for high throughput multi-dimensional blood cell analysis to identify non-traditional circulating biomarkers for clinical diagnostics.

Efficient Metal Inter-Layer Via Utilization Strategies for Three-dimensional Integrated Circuits

Abstract: Three-dimensional integrated circuit (3D-IC) technology gained prominence for future integrated chips (ICs) due to increased transistor density at the same technology node. Conventional 3D-IC implementation involves die stacking with vertical interconnects realized by through-silicon-via (TSV). One of the main challenges associated with 3D-IC technology is the TSV size since they are large in size (100-400x larger than standard cells in 45nm technology) and their diameters do not scale with technology. In addition, lot of dummy TSVs are inserted to satisfy minimum density rule laid by foundries which further increases the overhead. Also, a need for small form factor implementation of on-chip devices especially inductors are required for heterogeneous integration. In this paper, we discuss about utilizing TSVs to form on-chip inductors for various applications. On the other hand, monolithic Three-dimensional integrated circuit (M3D-IC) technology is enabled by sequential integration of substrate layers and the devices at different layers are connected by metal inter-layer via (MIV) where MIV passes through the silicon but the size very small compared with the TSV in 3D-ICs. The effective area occupied by MIV on the substrate will increase with the number of MIVs. Therefore, in this paper, we will discuss efficient strategies to reduce silicon footprint overhead by MIV through reconfiguration of silicon around MIV to design MIV-capacitor and MIV-transistor devices. TCAD simulations of 14nm channel length demonstrate that the proposed approach will reduce the silicon area of inverter by about 24% compared with the conventional approach for transistor-level M3D-IC technology.

Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration

Abstract: Metal inter-layer via (MIV) in Monolithic three-dimensional integrated circuits (M3D-IC) is used to connect inter-layer devices and provide power and clock signals across multiple layers. The size of MIV is comparable to logic gates because of the significant reduction in substrate layers due to sequential integration. Despite MIV’s small size, the impact of MIV on the performance of adjacent devices should be considered to implement IC designs in M3D-IC technology. In this work, we systematically study the changes in performance of transistors when they are placed near MIV to understand the effect of MIV on adjacent devices when MIV passes through the substrate. Simulation results suggest that the keep-out-zone (KOZ) for MIV should be considered to ensure the reliability of M3DIC technology and this KOZ is highly dependent on the M3DIC process. In this paper, we show that the transistor placed near MIV considering the M1 metal pitch as the separation will have up to 68, 668× increase in leakage current, when the channel doping is 1015cm−3, source/drain doping of 1018cm−3 and substrate layer height of 100 nm. We also show that, this increase in leakage current can also be reduced significantly by having KOZ around MIV, which is dependent on the process.

Design and development of multiphase buck converters for voltage regulator modules

Abstract: Modern microprocessors in high-power applications require a low input voltage and a high input current, necessitating the use of multiphase buck converters. As per microprocessor computing complexity, the power requirements of the switching converter will also be more important and will be increasing as per load demand. Previous studies introduced some methods to achieve the advantages associated with multiphase regulators. This paper presents an effective closed closed-loop control scheme for multiphase buck converters that reduces ripple and improves transient response. It is suitable for applications that require regulated output voltage with effectively reduced ripple. The analysis began with a simulation of the entire design using the OrCAD tool, followed by the construction of a hardware setup. Experiments on a 200 Khz, 9 V, 12 A, 2-phase buck voltage regulator were conducted and the proposed experiment found to be useful.