Other affiliations: International Institute of Information Technology, International Institute of Information Technology, Hyderabad, Indian Institutes of Technology
Bio: Madhu Mutyam is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Cache & Cache pollution. The author has an hindex of 12, co-authored 67 publications receiving 611 citations. Previous affiliations of Madhu Mutyam include International Institute of Information Technology & International Institute of Information Technology, Hyderabad.
Papers published on a yearly basis
TL;DR: It is proved that the P systems with context-free rules are computationally universal, able to generate all computable array languages.
Abstract: We consider array languages (sets of pictures consisting of symbols placed in the lattice points of the 2D grid) and the possibility to handle them with P systems. After proving binary normal forms for array matrix grammars (which, even in the case when no appearance checking is used, are known to generate the array languages of arbitrary array grammars), we prove that the P systems with context-free rules (with three membranes and no control on the communication or the use of rules) are computationally universal, able to generate all computable array languages. Some open problems are also formulated.
23 May 2001
TL;DR: A new variant of P systems, P systems with membrane creation, in which some objects are productive and create membranes is proposed, capable of solving the Hamiltonian Path Problem in linear time.
Abstract: P systems, introduced by Gh. Paun form a new class of distributed computing model. Several variants of P systems were already shown to be computationally universal. In this paper, we propose a new variant of P systems, P systems with membrane creation, in which some objects are productive and create membranes. This new variant of P systems is capable of solving the Hamiltonian Path Problem in linear time. We show that P systems with membrane creation are computationally complete.
05 Jan 2004
TL;DR: No Adjacent Transition (NAT) coding scheme is proposed, a bus encoding technique that simultaneously reduces power consumption and eliminates cross-talk in system-level buses.
Abstract: Considerable research has been done in the area of bus-encoding techniques, for either power minimization or cross-talk elimination in system-level buses, but not both together. We propose No Adjacent Transition (NAT) coding scheme, a bus encoding technique that simultaneously reduces power consumption and eliminates cross-talk. NAT-encoding and decoding algorithms are proposed and an analytical study of power dissipation is presented.
05 Jan 2004
TL;DR: It is shown that m-bit crosstalk delay free binary Fibonacci codewords are used to encode /spl lfloor/log/sub 2/(F/ sub m+2/)/spl rfloor/-bit bus, where F/sub m-2/ is the (m+2)/sup th/ Fib onacci number.
Abstract: As the CMOS technology scaled down to deep sub-micron level, the crosstalk effects due to the coupling capacitance between interconnection lines has become one of the main performance limiting factors. Several methods such as those based on routing strategies, skewing the timing of signals on adjacent wires, interleaving mutually exclusive buses, precharging the bus, and bus encoding technique, have been proposed to eliminate/reduce the crosstalk delay. In this work, we propose a bus encoding technique using a variant of binary Fibonacci representation to prevent crosstalk delay and give a recursive procedure to generate crosstalk delay free binary Fibonacci codewords. We show that m-bit crosstalk delay free binary Fibonacci codewords are used to encode /spl lfloor/log/sub 2/(F/sub m+2/)/spl rfloor/-bit bus, where F/sub m+2/ is the (m+2)/sup th/ Fibonacci number. So, a 32-bit bus can be encoded using 46-bit crosstalk delay free binary Fibonacci codewords.
14 Jun 2006
TL;DR: This paper proposes techniques based on load balancing across the integer functional units of VLIW architectures for balanced thermal behavior and peak temperature minimization, and reveals that the peak temperature can be reduced through compiler scheduling.
Abstract: As processors, memories, and other components of today's embedded systems are pushed to higher performance in more enclosed spaces, processor thermal management is quickly becoming a limiting design factor. While previous proposals mostly approached this thermal management problem from circuit and architecture angles, software can also play an important role in identifying and eliminating thermal hotspots as it is the main factor that shapes the order and frequency of accesses to different hardware components in the chip. This is particularly true for compiler-scheduled Very Long Instruction Word (VLIW) datapath.In this paper, we focus on a compiler-based approach to make the thermal profile more balanced in the integer functional units of VLIW architectures. For balanced thermal behavior and peak temperature minimization, we propose techniques based on load balancing across the integer functional units with or without rotation of functional unit usage. As leakage power is exponentially dependent on temperature and temperature is dependent on total power (i.e., switching and leakage), in our techniques, we also consider leakage power optimization by IPC tuning (instructions issued per cycle). By taking a code that is already scheduled for maximum performance as input, our scheduling strategies modify this performance-oriented schedule for balanced thermal behavior with negligible performance degradation. We simulate our scheduling strategies using a framework that consists of the Trimaran infrastructure, a power model, and the HotSpot. Our experimental results using several benchmark programs reveal that the peak temperature can be reduced through compiler scheduling.
01 Jan 2010
TL;DR: This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification, as well as other topics relevant to the design of parallel CAD algorithms and software tools.
Abstract: High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.
TL;DR: The present paper presents the basic ideas of computing with membranes and some fundamental properties (mostly concerning the computational power and efficiency) of P systems of various types.
Abstract: Membrane systems are models of computation which are inspired by some basic features of biological membranes. In a membrane system multisets of objects are placed in the compartments defined by the membrane structure, and the objects evolve by means of "reaction rules" also associated with the compartments, and applied in a maximally parallel, nondeterministic manner. The objects can pass through membranes, the membranes can change their permeability, they can dissolve, and they can divide. These features are used in defining transitions between configurations of the system, and sequences of transitions are used to define computations. In the case of symbol-objects, we compute a set of numbers, and in the case of string-objects we compute a set of strings, hence a language. Many different classes of such computing devices (now called P systems) have already been investigated. Most of them are computationally universal, i.e., equal in power to Turing machines. Systems with an enhanced parallelism are able to trade space for time and solve in this way (at least in principle), by making use of an exponential space, intractable problems in a feasible time.The present paper presents the basic ideas of computing with membranes and some fundamental properties (mostly concerning the computational power and efficiency) of P systems of various types.
08 Nov 2008
TL;DR: The results show that the proposed cache architecture has low miss rates comparable to a highly associative cache and short access times and power efficiency close to that of a direct-mapped cache, and can thwart cache-based software side-channel attacks, providing both legacy and security-enhanced software a much higher degree of security.
Abstract: Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent findings on efficient attacks based on information leakage in caches have also brought the security issue up front. Design for security introduces even more restrictions and typically leads to significant performance degradation. This paper presents a novel cache architecture that can simultaneously achieve the above goals. Specifically, cache miss rates are reduced with dynamic remapping and longer cache indices, access-time overhead overcome with astute low-level circuit design, and information leakage thwarted by a security-aware cache replacement algorithm together with the performance enhancing mechanisms. We present both theoretical analysis and experimental results, using the SPEC2000 suite to evaluate the cache miss behavior, and CACTI and HSPICE to validate the circuit design. Our results show that the proposed cache architecture has low miss rates comparable to a highly associative cache and short access times and power efficiency close to that of a direct-mapped cache. At the same time it can thwart cache-based software side-channel attacks, providing both legacy and security-enhanced software a much higher degree of security. Additional benefits that the proposed cache architecture can bring, like fault tolerance and hot-spot mitigation, are also discussed briefly.
01 Jan 2008
TL;DR: This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design, and will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on- chip communication architectures.
Abstract: Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures. KEY FEATURES * A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends * Detailed analysis of all popular standards for on-chip communication architectures * Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts * Future trends that with have a significant impact on research and design of communication architectures over the next several years