Mahendra Rathor

Bio: Mahendra Rathor is an academic researcher from Indian Institute of Technology Indore. The author has contributed to research in topics: Steganography & Hardware acceleration. The author has an hindex of 4, co-authored 20 publications receiving 47 citations. Previous affiliations of Mahendra Rathor include Indian Institutes of Technology.

IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems

Abstract: Intellectual property (IP) core of digital signal processing (DSP) kernels act as hardware accelerators in consumer electronics (CE) systems However due to rising threats of cloning and counterfeiting to an IP core, security remains an important subject of research for these hardware accelerators This paper presents a novel key-driven hash-chaining based hardware steganography for securing such IP cores used in CE systems The proposed approach is capable to implant secret invisible stego-marks in design using hash-chaining process that incorporates switches, strong large stego-keys, multiple encoding algorithms and hash blocks The methodology proposed provides massive security against IP cloning and counterfeiting while incurring nominal design overhead (<03 %) The results of the proposed approach on comparison with state of the art indicated significantly stronger digital evidence (lower probability of co-incidence), stronger key size (in bits) and lower design cost using proposed stego-marks Further, from an attacker’s perspective, the proposed steganography increases an attacker’s effort manifold during decoding the valid stego-key value (for generating/extracting original secret stego-mark), compared to existing approaches

Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging Systems

Abstract: In modern healthcare technology involving diagnosis through medical imaging systems, compression and data transmission play a pivotal role. Medical imaging systems play an indispensable role in several medical applications where camera/scanners generate compressed images about a patient’s internal organ and may further transmit it over the internet for remote diagnosis. However, tampered or corrupted compressed medical images may result in wrong diagnosis of diseases leading to fatal consequences. This paper aims to secure the underlying JPEG compression processor used in medical imaging systems that generates the compressed medical images for diagnosis. The proposed work targets to secure the JPEG compression processor against well-acknowledged threats such as counterfeiting/cloning and Trojan insertion using double line of defense through integration of robust structural obfuscation and hardware steganography. The second line of defense incorporates stego-key based hardware steganography that augments the following: non-linear bit manipulation using S-box (confusion property), diffusion property, alphabetic encryption, alphabet substitution, byte concatenation mode, bit-encoding (converting into stego-constraints) and embedding constraints. The results of the proposed approach achieve robust security in terms of significant strength of obfuscation, strong stego-key size (775 bits for JPEG compression processor and 610 bits for JPEG DCT core) and probability of coincidence of 9.89e-8, at nominal design cost.

IP Core Steganography for Protecting DSP Kernels Used in CE Systems

Abstract: Intellectual Property (IP) core protection of Digital Signal Processing (DSP) kernels is an important subject of research for Consumer Electronics (CE) systems. An IP core may be prone to piracy, forgery and counterfeiting. The need of the hour is developing effective technique that is robust and incurs low overhead to detect IP core infringement. This paper presents a novel ‘IP core steganography’ methodology for DSP kernels that is capable of detecting IP piracy. The proposed methodology is capable of implanting concealed information into the existing IP core design of DSP datapath without using any external signature, to reflect the IP core ownership. The presented ‘IP core steganography’ methodology is non-intuitive in nature indicating that the intended secret information does not attract attention to itself from an adversary’s perspective. The implanted information incurs almost no design overhead and yields lower design cost than signature-based IP core protection techniques. Further, in the presented approach the amount of concealed information embedded is fully designer controlled through a ‘thresholding’ parameter, unlike signature-based techniques where signature pattern impacts the robustness and overhead. Results of proposed approach yielded lower cost and stronger proof of authorship compared to a signature-based approach.

Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting

Abstract: This article presents a novel methodology to secure hardware accelerators (such as digital signal processing (DSP) and multimedia intellectual property (IP) cores) against ownership threats/IP piracy using biometric fingerprinting. In this approach, an IP vendor’s biometric fingerprint is first converted into a corresponding digital template, followed by embedding fingerprint’s digital template into the design in the form of secret biometric constraints; thereby generating a secured hardware accelerator design. The results report the following qualitative and quantitative analysis of the proposed biometric fingerprint approach: 1) impact of 11 different fingerprints on probability of coincidence (Pc) metric. As evident, the proposed approach achieves a very low Pc value in the range of 2.22E−3 to 4.35E−6. Further, the biometric fingerprint achieves total constraints size between minimum 350 bits to maximum 895 bits; 2) impact of six different resource constraints on the design cost overhead of JPEG compression hardware postembedding biometric fingerprint. As evident, for all the resource constraints implemented, the design cost overhead is 0%; and 3) comparative analysis of proposed biometric fingerprint with recent work, for five different signature strength values, in terms of Pc. As evident, the proposed approach achieves minimum 3.9E+2 times and maximum 6.9E+4 times lower Pc, when compared to recent work.

Enhanced Security of DSP Circuits Using Multi-Key Based Structural Obfuscation and Physical-Level Watermarking for Consumer Electronics Systems

Abstract: Security of Digital Signal Processing (DSP) based Intellectual Property (IP) core is very important for the overall security and reliability of Consumer Electronics (CE) systems. These DSP based IP cores are highly vulnerable to threats such as reverse engineering (RE) leading to Trojan insertion, counterfeiting and cloning. Thus developing robust defense mechanisms is highly significant for these DSP circuits used in CE systems, especially to thwart the aforesaid threats. This article presents for the first time a double line of defense mechanism using robust multi-key based structural obfuscation integrated with tamper-tolerant physical level watermarking to counter such hardware threats. The proposed approach introduces novel key-driven partitioning based obfuscation and key-driven folding knob based obfuscation, along with other key-driven transformation based obfuscations. Additionally, the proposed approach presents novel multi-variable signature encoding based physical-level watermarking on key-based structurally obfuscated DSP circuits. The presented double line of defense incurs zero overhead as well yields high tamper tolerance during hardware watermarking. The proposed approach yields stronger strength of obfuscation, lower probability of co-incidence and larger key-space at low design cost against attacks.

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Abstract: Hardware security and trust have become a pressing issue during the last two decades due to the globalization of the semiconductor supply chain and ubiquitous network connection of computing devices. Computing hardware is now an attractive attack surface for launching powerful cross-layer security attacks, allowing attackers to infer secret information, hijack control flow, compromise system root-of-trust, steal intellectual property (IP), and fool machine learners. On the other hand, security practitioners have been making tremendous efforts in developing protection techniques and design tools to detect hardware vulnerabilities and fortify hardware design against various known hardware attacks. This article presents an overview of hardware security and trust from the perspectives of threats, countermeasures, and design tools. By introducing the most recent advances in hardware security research and developments, we aim to motivate hardware designers and electronic design automation tool developers to consider the new challenges and opportunities of incorporating an additional dimension of security into robust hardware design, testing, and verification.

Finger Vein Recognition Algorithm Based on Lightweight Deep Convolutional Neural Network

Abstract: Even though the deep neural networks have strong feature representation capability and high recognition accuracy in finger vein recognition, the deep models are computationally intensive and poor in timeliness. To address these issues, this article proposes a lightweight algorithm for finger vein image recognition and matching. The proposed algorithm uses a lightweight convolutional model in the backbone network and employs a triplet loss function to train the model, which not only improves the matching accuracy, but also satisfies the real-time matching requirements. In addition, the Mini-region of interest (RoI) and finger vein pattern feature extraction also effectively solve the problems of large amounts of calculation and background noise. Moreover, the present model recognizes new categories based on the feature vector space constructed by the finger vein recognition system, so that new categories can be recognized without retraining the model. The results show that the finger vein recognition and matching algorithm proposed in this article achieves 99.3% and 99.6% in recognition accuracy and 14.2 and 16.5 ms in matching time for the dataset Shandong University Machine Learning and Applications Laboratory-Homologous Multimodal Biometric Traits (SDUMLA-HMT) and Peking University Finger Vein Dataset (PKU-FVD), respectively. These metrics show that our approach is time-saving and more effective than previous algorithms. Compared with the state-of-the-art finger vein recognition algorithm, the proposed algorithm improves 1.45% in recognition accuracy while saving 45.7% in recognition time.

Cipher Block Chaining Support Vector Machine for Secured Decentralized Cloud Enabled Intelligent IoT Architecture

Abstract: The growth of internet era leads to a major transformation in a storage of data and accessing the applications. One such new trend that promises the endurance is the Cloud computing. Computing resources offered by the Cloud includes the servers, networks, storage, and applications, all as services. With the advent of Cloud, a single application is delivered as a metered service to numerous users, via an Application Programming Interface (API) accessible over the network. The services offered via the Cloud are such as the infrastructure, software, platform, database and web services. The main motivation of this application model is to provide computationally secure key generation to protect the data via encryption. This key generation in the cryptography process falls into three categories in this research work. In the first part, SVM based encryption service model is constructed for which the key generation is from the conventional encryption operation mode with some improvements. To make the process more complex, the optimization techniques are taken into account for the key generation in descendant two methods application model that acts computationally more secure specifically for Cloud environment. The results of security analysis confirm the effectiveness of the proposed application model withstands potentially against various attacks such as Chosen Cipher Attack, Chosen Plain text Attack indistinguishable attacks for files. In case of images, it resists well against statistical and differential attacks. Comparative Analysis shows evidence of the efficiency of the developed pioneering application model quality and strength compared with that of the existing services.

eChain: A Blockchain-Enabled Ecosystem for Electronic Device Authenticity Verification

Abstract: Counterfeit electronic devices can cause a significant revenue loss and brand value damage to the original component manufacturers (OCM). In addition, they can instigate serious safety and security issues in critical military and space applications. These devices can be injected by untrusted entities in the supply chain, such as outsourced foundries, distributors, PCB assemblers, and system integrators. Existing methods for device authenticity verification are either destructive, require an advanced electrical test or physical inspection infrastructure. Furthermore, the existing database query-based verification systems by OCMs provide an illusion of authenticity verification by looking for a device record in their online system. In reality, a customer may have bought a cloned or recycled copy of an electronic device and may find a valid record in the OCM verification system. This paper presents a blockchain-centric solution to address these limitations to verify electronic devices. A detailed study is presented to transform an existing supply chain into a trustworthy distributed ledger framework called eChain (electronic Chain). eChain generates device provenance records from blockchain that users can utilize to classify authentic and counterfeit ICs. A fully functional prototype of eChain is developed to demonstrate the feasibility and efficacy of the proposed solution.

IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems

Abstract: Intellectual property (IP) core of digital signal processing (DSP) kernels act as hardware accelerators in consumer electronics (CE) systems However due to rising threats of cloning and counterfeiting to an IP core, security remains an important subject of research for these hardware accelerators This paper presents a novel key-driven hash-chaining based hardware steganography for securing such IP cores used in CE systems The proposed approach is capable to implant secret invisible stego-marks in design using hash-chaining process that incorporates switches, strong large stego-keys, multiple encoding algorithms and hash blocks The methodology proposed provides massive security against IP cloning and counterfeiting while incurring nominal design overhead (<03 %) The results of the proposed approach on comparison with state of the art indicated significantly stronger digital evidence (lower probability of co-incidence), stronger key size (in bits) and lower design cost using proposed stego-marks Further, from an attacker’s perspective, the proposed steganography increases an attacker’s effort manifold during decoding the valid stego-key value (for generating/extracting original secret stego-mark), compared to existing approaches