Frequencies from 100 GHz to 3 THz are promising bands for the next generation of wireless communication systems because of the wide swaths of unused and unexplored spectrum. These frequencies also offer the potential for revolutionary applications that will be made possible by new thinking, and advances in devices, circuits, software, signal processing, and systems. This paper describes many of the technical challenges and opportunities for wireless communication and sensing applications above 100 GHz, and presents a number of promising discoveries, novel approaches, and recent results that will aid in the development and implementation of the sixth generation (6G) of wireless networks, and beyond. This paper shows recent regulatory and standard body rulings that are anticipating wireless products and services above 100 GHz and illustrates the viability of wireless cognition, hyper-accurate position location, sensing, and imaging. This paper also presents approaches and results that show how long distance mobile communications will be supported to above 800 GHz since the antenna gains are able to overcome air-induced attenuation, and present methods that reduce the computational complexity and simplify the signal processing used in adaptive antenna arrays, by exploiting the Special Theory of Relativity to create a cone of silence in over-sampled antenna arrays that improve performance for digital phased array antennas. Also, new results that give insights into power efficient beam steering algorithms, and new propagation and partition loss models above 100 GHz are given, and promising imaging, array processing, and position location results are presented. The implementation of spatial consistency at THz frequencies, an important component of channel modeling that considers minute changes and correlations over space, is also discussed. This paper offers the first in-depth look at the vast applications of THz wireless products and applications and provides approaches for how to reduce power and increase performance across several problem domains, giving early evidence that THz techniques are compelling and available for future wireless communications.

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Wireless Communications and Applications Above 100 GHz: Opportunities and Challenges for 6G and Beyond

In-band full-duplex (IBFD) technology can enable unique system capabilities and network architectures by allowing devices to transmit and receive on the same frequency at the same time. While previously considered impossible, this ability can now be used to optimize resource sharing within the crowded frequency spectrum for various communication systems, including 5G new radio. The potential of these IBFD systems can only be realized if each device incorporates a sufficient number of self-interference cancellation techniques to ensure that its receivers do not saturate. This tutorial survey offers the most comprehensive collection to date of these techniques and discusses how all of them can be implemented within the different domains of a typical transceiver. In addition, the results of a novel IBFD system study are presented for more than 50 demonstrated communication systems with more than 80 different measurement scenarios. The various system parameters are then combined into a new figure of merit, which can be used to propel future research and accelerate the inclusion of IBFD technology within an upcoming wireless standard.

In-Band Full-Duplex Technology: Techniques and Systems Survey

Open, Programmable, and Virtualized 5G Networks: State-of-the-Art and the Road Ahead

This paper focuses on COSMOS - Cloud enhanced Open Software defined MObile wireless testbed for city-Scale deployment. The COSMOS testbed is being deployed in West Harlem (New York City) as part of the NSF Platforms for Advanced Wireless Research (PAWR) program. It will enable researchers to explore the technology "sweet spot" of ultra-high bandwidth and ultra-low latency in the most demanding real-world environment. We describe the testbed's architecture, the design and deployment challenges, and the experience gained during the design and pilot deployment. Specifically, we describe COSMOS' computing and network architectures, the critical building blocks, and its programmability at different layers. The building blocks include software-defined radios, 28 GHz millimeter-wave phased array modules, optical transport network, core and edge cloud, and control and management software. We describe COSMOS' deployment phases in a dense urban environment, the research areas that could be studied in the testbed, and specific example experiments. Finally, we discuss our experience with using COSMOS as an educational tool.

Challenge: COSMOS: A city-scale programmable testbed for experimentation with advanced wireless

The Open Radio Access Network (RAN) and its embodiment through the O-RAN Alliance specifications are poised to revolutionize the telecom ecosystem. O-RAN promotes virtualized RANs where disaggregated components are connected via open interfaces and optimized by intelligent controllers. The result is a new paradigm for the RAN design, deployment, and operations: O-RAN networks can be built with multi-vendor, interoperable components, and can be programmatically optimized through a centralized abstraction layer and data-driven closed-loop control. Therefore, understanding O-RAN, its architecture, its interfaces, and workflows is key for researchers and practitioners in the wireless community. In this article, we present the first detailed tutorial on O-RAN. We also discuss the main research challenges and review early research results. We provide a deep dive of the O-RAN specifications, describing its architecture, design principles, and the O-RAN interfaces. We then describe how the O-RAN RAN Intelligent Controllers (RICs) can be used to effectively control and manage 3GPP-defined RANs. Based on this, we discuss innovations and challenges of O-RAN networks, including the Artificial Intelligence (AI) and Machine Learning (ML) workflows that the architecture and interfaces enable, security, and standardization issues. Finally, we review experimental research platforms that can be used to design and test O-RAN networks, along with recent research results, and we outline future directions for O-RAN development.

Understanding O-RAN: Architecture, Interfaces, Algorithms, Security, and Research Challenges

A fundamental challenge of full-duplex (FD) wireless [1] is the implementation of low-cost, small-form-factor, integrated shared-antenna (ANT) interfaces with low loss, low noise, high TX-RX isolation, and large TX power handling. Providing more TX-RX isolation in the ANT interface that is robust to environmental variations lowers the self-interference cancellation (SIC) and dynamic range required in the RF, analog baseband (BB), and digital domains. Reciprocal shared-ANT interfaces, such as electrical-balance duplexers [2], fundamentally feature at least 3dB loss (practically >4dB). A non-reciprocal active shared-ANT duplexing scheme was demonstrated in [3], but such active approaches are limited in their maximum supported TX power (−17.3dBm in [3] limited by RX compression) and noise performance. An integrated FD RX with a magnetic-free non-reciprocal passive circulator was demonstrated in [4]. Despite the circulator's low loss and relatively high linearity, the RX could only handle up to −7dBm TX power due to limited circulator isolation and RX LNA linearity. NF under cancellation was also as high as 10.9dB.

18.2 Highly-linear integrated magnetic-free circulator-receiver for full-duplex wireless

Previously, we presented a non-magnetic, non-reciprocal N-path-filter-based circulator-receiver (circ.-RX) architecture for single-frequency full-duplex (SF-FD) wireless, which merges a commutation-based linear periodically time-varying (LPTV) non-magnetic circulator with a down-converting mixer and directly provides the baseband (BB) RX signals at its output, while suppressing the noise contribution of one set of the commutating switches. The architecture also incorporates an on-chip balance network to enhance the transmitter (TX)-RX isolation. In this paper, we present a detailed analysis of the architecture, including a noise analysis and an analysis of the effect of the balance network. The analyses are verified by the simulation and measurement results of a 65-nm CMOS 750-MHz circ.-RX prototype. The circ.-RX can handle up to +8 dBm of TX power with 8-dB noise figure (NF) and 40-dB average isolation over 20-MHz radio frequency (RF) bandwidth (BW). In conjunction with digital self-interference (SI) and its third-order intermodulation (IM3) cancellation, the SF-FD circ.-RX demonstrates 80-dB overall SI suppression for up to +8-dBm TX average output power. The claims are also verified through an SF-FD demonstration where a −50-dBm weak desired received signal is recovered while transmitting a 0-dBm average power orthogonal frequency-division multiplexing (OFDM)-like TX signal.

Analysis and Design of Commutation-Based Circulator-Receivers for Integrated Full-Duplex Wireless

Full-duplex (FD) wireless can significantly enhance spectrum efficiency but requires tremendous amount of self-interference (SI) cancellation. Recent advances in the RFIC community enabled wideband RF SI cancellation (SIC) in integrated circuits (ICs) via frequency-domain equalization (FDE), where RF filters channelize the SI signal path. Unlike other FD implementations, that mostly rely on delay lines, FDE-based cancellers can be realized in small-form-factor devices. However, the fundamental limits and higher layer challenges associated with these cancellers were not explored yet. Therefore, and in order to support the integration with a software-defined radio (SDR) and to facilitate experimentation in a testbed with several nodes, we design and implement an FDE-based RF canceller on a printed circuit board (PCB). We derive and experimentally validate the PCB canceller model and present a canceller configuration scheme based on an optimization problem. We then extensively evaluate the performance of the FDE-based FD radio in the SDR testbed. Experiments show that it achieves 95dB overall SIC (52dB from RF SIC) across 20MHz bandwidth, and an average link-level FD gain of 1.87x. We also conduct experiments in: (i) uplink-downlink networks with inter-user interference, and (ii) heterogeneous networks with half-duplex and FD users. The experimental FD gains in the two types of networks confirm previous analytical results. They depend on the users' SNR values and the number of FD users, and are 1.14x-1.25x and 1.25x-1.73x, respectively. Finally, we numerically evaluate and compare the RFIC and PCB implementations and study various design tradeoffs.

https://dl.acm.org/doi/pdf/10.1145/3300061.3300138

Wideband Full-Duplex Wireless via Frequency-Domain Equalization: Design and Experimentation

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18 μτη CMOS technology, prove that the proposed circuit reduces the power consumption by a factor of two and reduces comparison time as large as 210ps in the same budget of offset voltage compared to the conventional circuit. Moreover, the offset voltage and power consumption of the comparator trades with the speed which is simply controlled by the delay of the second stage. As a result, a low-power comparator for given offset and speed requirements can be designed efficiently.

A low-power high-speed comparator for analog to digital converters

In this paper, we show how phased-array beamforming can be synergistically combined with full-duplex (FD) to achieve wideband RF self-interference (SI) suppression with minimal link budget (transmitter (TX) and receiver (RX) array gain) penalty and with no additional power consumption. An N-path-filter-based circulator-receiver FD front-end enables phased-array beamforming at baseband with minimal overhead by virtue of its multi-phase outputs. A 65nm CMOS scalable 4-element full-duplex circulator-receiver array is demonstrated that repurposes spatial beamforming degrees of freedom (DoFs) to achieve SI suppression, enabling (i) 50dB overall RF array self-interference cancellation (SIC) over 16.25MHz (WiFi-like) bandwidth (BW) with less than 3.5/3dB degradation in TX and RX array gains, respectively, across 8 elements, and (ii) 100dB overall array SIC suppression including digital SIC at + 16.5dBm TX array power handling.

Mahmood Baraani Dastjerdi

Papers

18.2 Highly-linear integrated magnetic-free circulator-receiver for full-duplex wireless

Analysis and Design of Commutation-Based Circulator-Receivers for Integrated Full-Duplex Wireless

Wideband Full-Duplex Wireless via Frequency-Domain Equalization: Design and Experimentation

A low-power high-speed comparator for analog to digital converters

Full Duplex Circulator-Receiver Phased Array Employing Self-Interference Cancellation via Beamforming