Makoto Miyamura

Bio: Makoto Miyamura is an academic researcher from NEC. The author has contributed to research in topics: Crossbar switch & Programmable logic device. The author has an hindex of 16, co-authored 92 publications receiving 775 citations.

Semiconductor device, integrated circuit, and semiconductor manufacturing method

Abstract: A semiconductor circuit has a plurality of MISFETs formed with channel films comprised of semiconductor layers on an insulation film. Channel film thicknesses of each MISFET are different. A correlation relationship is fulfilled where concentration per unit area of impurity contained in the channel films becomes larger for MISFETs of a thicker channel film thickness. As a result, it is possible to suppress deviation of threshold voltage caused by changes in channel film thickness. In this event, designed values for the channel film thicknesses of the plurality of MISFETs are preferably the same, and the difference in channel film thickness of each MISFET may depend on statistical variation from the designed values. The concentration of the impurity per unit area is proportional to the channel film thickness, or is a function that is convex downwards with respect to the channel film thickness.

Polymer Solid-Electrolyte Switch Embedded on CMOS for Nonvolatile Crossbar Switch

Abstract: A polymer solid-electrolyte (PSE) switch has been embedded in a 90-nm-node CMOS featuring a forming-less programming and extremely high on/off ratio of 105. A fast programming of 10 ns is also demonstrated for 50-nmΦ 1 k-b array by introducing the PSE switches integrated with a fully logic compatible process below 350°C. A high free volume in the PSE is supposed to result in the smooth formation of the Cu bridge without destroying the electrolyte, thereby also resulting in forming-less programming and high breakdown voltage. High disturbance reliability (T50; 50% fail) is extracted to be over 10 years at operation condition. The improved switching characteristics enable us to accurately program the crossbar circuit in a practical scale (32 × 32) without cell transistors. The developed switch is a strong candidate for realizing a low-power and low-cost nonvolatile programmable logic.

Semiconductor device and manufacturing method for semiconductor device

Abstract: A semiconductor device includes multilayer interconnects and two variable resistance elements (22 a, 22 b) that are provided among the multilayer interconnects and that include first electrodes (5), second electrodes (10 a, 10 b), and variable resistance element films (9 a, 9 b) that are each interposed between first electrodes (5) and respective second electrodes (10 a, 10 b). Either the first electrodes (5) or the second electrodes (10 a, 10 b) of the two variable resistance elements (22 a, 22 b) are unified.

Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS

Abstract: Programmable devices such as SRAM-based FPGAs have the major challenges of power consumption and circuit area due to the excessive standby leakage current and the threshold voltage variation in highly scaled SRAM. Back-end-of-line (BEOL) device, which is integrated in the interconnect layers, is attractive for reducing the performance gap between FPGA and cell-based ASIC [1–4]. In this paper, we demonstrate the fundamental operations of a programmable cell array and a 32×32 crossbar switch using a nonvolatile and rewritable solid-electrolyte switch (nanobridge or NB). A 72% reduction in chip-area compared with that of a standard-cell-based design is achieved on a 90nm CMOS platform.

First demonstration of logic mapping on nonvolatile programmable cell using complementary atom switch

Abstract: Reconfigurable nonvolatile programmable logic using complementary atom switch (CAS) is successfully demonstrated on a 65-nm-node test chip. Various logics are realized by synthesizing RTL codes and mapping the configurations into CAS-based programmable cell array. Each cell includes the two 4-input LUTs, 19×16 crossbar switch, and 368-b CAS. The CAS integrated over CMOS reduces the cell area by 78% compared to a conventional SRAM-based design.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

Abstract: Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Semiconductor device and display device

Abstract: An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

Effect of nitrogen on band alignment in HfSiON gate dielectrics

Abstract: Nitridation of HfSiO films improves certain physical and electrical properties—when using gate stack layers—such as their crystallization temperature and their resistance to interdiffusion. We have studied the band alignment of HfSiO and HfSiON films by soft x-ray photoemission, oxygen K-edge x-ray absorption, and spectroscopic ellipsometry. Nitridation of HfSiO reduced the band gap by 1.50eV±0.05eV, and the valence- and conduction-band offsets by 1.2eV±0.1eV and 0.33eV±0.05eV, respectively. Although the band-gap reduction should lead to increased leakage, the barrier heights are still sufficient for proposed near-future complementary metal-oxide-semiconductor applications.

Review on high-k dielectrics reliability issues

Abstract: High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.

Overview and status of metal S/D Schottky-barrier MOSFET technology

Abstract: In this paper, the metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology is reviewed. The technology offers several benefits that enable scaling to sub-30-nm gate lengths including extremely low parasitic S/D resistance (1% of the total device resistance), atomically abrupt junctions that enable the physical scaling of the device to sub-10-nm gate lengths, superior control of OFF-state leakage current due to the intrinsic Schottky potential barrier, and elimination of parasitic bipolar action. These and other benefits accrue using a low-thermal-budget CMOS manufacturing process requiring two fewer masks than conventional bulk CMOS. The SB-CMOS manufacturing process enables integration of critical new materials such as high-k gate insulators and strained silicon substrates. SB MOSFET technology state of the art is also reviewed, and shown to be focused on barrier-height-lowering techniques that use interfacial layers between the metal S/Ds and the channel region. SB-PMOS devices tend to have superior performance compared to NMOS, but NMOS performance has recently improved by using ytterbium silicide or by using hybrid structures that incorporate interfacial layers to lower the SB height.