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Maksim Jenihhin

Other affiliations: Tallinn University
Bio: Maksim Jenihhin is an academic researcher from Tallinn University of Technology. The author has contributed to research in topics: Computer science & Fault coverage. The author has an hindex of 10, co-authored 122 publications receiving 500 citations. Previous affiliations of Maksim Jenihhin include Tallinn University.


Papers
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20 Apr 2016
Abstract: ..................................................................................................... 90 KOKKUVÕTE .................................................................................................. 92 ACKNOWLEDGEMENTS ............................................................................... 94 Appendix A ........................................................................................................ 95 Appendix B ...................................................................................................... 103 Appendix C ...................................................................................................... 109 Appendix D ...................................................................................................... 117 Appendix E ...................................................................................................... 125 Appendix F ...................................................................................................... 133

55 citations

Proceedings ArticleDOI
28 May 2012
TL;DR: An automated approach to correcting system-level designs with dynamic-slicing and location-ranking-based method for accurately pinpointing the error locations combined with a dedicated set of mutation operators for automatically proposing corrections to the errors.
Abstract: Verification is increasingly becoming the bottleneck in designing digital systems. In fact, most of the verification cycle is not spent on detecting the occurrences of errors but on debugging, consisting of locating and correcting the errors. However, automated design-error debug, especially at the system-level, has received far less attention than error detection. Current paper presents an automated approach to correcting system-level designs. We propose dynamic-slicing and location-ranking-based method for accurately pinpointing the error locations combined with a dedicated set of mutation operators for automatically proposing corrections to the errors. In order to validate the approach, experiments on the Siemens benchmark set have been carried out. The experiments show that the proposed method is able to correct three times more errors compared to the state-of-the-art mutation-based correction methods while examining fewer mutants.

24 citations

Proceedings ArticleDOI
Gert Jervan1, Petru Eles1, Zebo Peng1, Raimund Ubar, Maksim Jenihhin 
03 Nov 2003
TL;DR: This paper proposes a methodology to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized.
Abstract: This paper presents a solution to the test tone minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudo-random test patterns that are generated online, and deterministic test patterns that are generated offline and stored in the system. We propose a methodology to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.

23 citations

Proceedings ArticleDOI
01 Oct 2012
TL;DR: Experimental results on very large designs show that zamiaCAD compares favorable to other frameworks with respect to the scalability aspects, and an evaluation of the model for static analysis as one of the back-end applications is presented.
Abstract: As of today, RTL still remains the primary abstraction level for VLSI SoC design entry and state-of-the-art design flows need to cope with designs of enormous size, and thus, to scale well. This paper presents an open-source framework zamiaCAD based on a scalable model that includes both, a comprehensive elaboration front-end for RTL design and design processing back-end flows. The persistence and scalability are guaranteed by a custom-designed and highly optimized object database. As an HDL-centric framework it follows the concept of non-intrusiveness. In this paper, we discuss in detail the concepts of design elaboration into the scalable design model and present an evaluation of the model for static analysis as one of the back-end applications. Experimental results on very large designs show that zamiaCAD compares favorable to other frameworks with respect to the scalability aspects.

17 citations

Journal ArticleDOI
TL;DR: A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed, based on intensive SPICE simulations of individual gates and the generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTi-induced path delay.
Abstract: The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit's permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics.

16 citations


Cited by
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01 Jan 2015
TL;DR: The abstract should follow the structure of the article (relevance, degree of exploration of the problem, the goal, the main results, conclusion) and characterize the theoretical and practical significance of the study results.
Abstract: Summary) The abstract should follow the structure of the article (relevance, degree of exploration of the problem, the goal, the main results, conclusion) and characterize the theoretical and practical significance of the study results. The abstract should not contain wording echoing the title, cumbersome grammatical structures and abbreviations. The text should be written in scientific style. The volume of abstracts (summaries) depends on the content of the article, but should not be less than 250 words. All abbreviations must be disclosed in the summary (in spite of the fact that they will be disclosed in the main text of the article), references to the numbers of publications from reference list should not be made. The sentences of the abstract should constitute an integral text, which can be made by use of the words “consequently”, “for example”, “as a result”. Avoid the use of unnecessary introductory phrases (eg, “the author of the article considers...”, “The article presents...” and so on.)

1,229 citations

Proceedings Article
01 Jan 1988
TL;DR: FXT as mentioned in this paper is a software tool which implements inductive fault analysis for CMOS circuits and extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence.
Abstract: FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.<>

244 citations

01 Jan 2016
TL;DR: The logical effort designing fast cmos circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for reading logical effort designing fast cmos circuits. As you may know, people have search numerous times for their chosen novels like this logical effort designing fast cmos circuits, but end up in infectious downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they are facing with some harmful bugs inside their desktop computer. logical effort designing fast cmos circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our book servers hosts in multiple locations, allowing you to get the most less latency time to download any of our books like this one. Merely said, the logical effort designing fast cmos circuits is universally compatible with any devices to read.

137 citations