IEEE Antennas and Wireless Propagation Letters

This paper presents an assessment of jitter induced by power and ground (P/G) voltage variations. The assessment is based on an extended input/output buffer information specification (IBIS)-like model for capturing the effect of P/G signal variations under simultaneous switching output (SSO) buffers. The requirements of nonlinear modeling for the accurate prediction is explained and illustrated. The implemented large signal equivalent-circuit model is validated under different test conditions having different P/G voltage variations for predicting the output signal distortions. The associated jitter analysis by predicting the eye diagram under the noise conditions is performed. The maximum values of the prediction error for the peak to peak values of eye jitter and eye height are 7.06% and 2.59%, respectively.

An IBIS-like Modelling for Power/Ground Noise Induced Jitter under Simultaneous Switching Outputs (SSO)

This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc.

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A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

This article presents two methods, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittance matrix. The proposed methods are used to develop a generalised two-port network analysis for the commonly used amplifier topologies, in the presence of the supply, ground, bulk, and input noise sources. Various illustrative case studies (common-source, common-gate, and push-pull amplifiers) are considered to validate the analytical method of different CMOS technology nodes (180 nm, 110 nm, and 28 nm) and foundries (Lfoundry, UMC, and TSMC). Both the proposed methods are compared with the relevant existing methods in terms of mean percentage error (MPE), and computational complexity. The mathematically derived expressions using two methods show less than 4% MPE when compared with the schematic simulation results, obtained by the SPICE based simulations. Also, the post-layout simulations (PLS) results for all the examples (designed in CMOS 180 nm Lfoundry technology) show excellent matching with schematic simulations. The proposed methods can be further applicable to antennas, complex circuits, digital circuits, etc.

Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix

This paper addresses the problem of fast transient simulation of high-speed coupled channels driven by transceivers that include transmitter feed-forward equalization (TX-FFE). Practical circuit hardware implementations of such drivers may not be correctly represented by industry-standard algorithmic modeling interfaces (AMIs), which are usually based on ideal digital finite impulse response filters. In particular, slow transients may arise when aggressive FFE is activated and particular switching sequences significantly stress local voltage regulators integrated in the output buffers. In this paper, we model this effect using a constructive hierarchical approximation of the analog waveforms that form a linearized vector Thevenin or Norton representation of the driver. This representation enables the accurate simulation of coupled channels including both differential- and common-mode signals. Analog waveforms at the receiver input are readily obtained by standard time-frequency transformations while including channel characteristics and any additional linear equalization block, if present. This proposed framework is compatible with industry-standard AMIs, extending their scope to coupled channels with nonideal TX-FFE circuit blocks. Eye diagrams and transient waveforms corresponding to millions of bits are computed in few seconds using a nonoptimized software implementation. Random jitter and crosstalk are seemlessly included as in standard AMI frameworks. The results of various numerical experiments on commercial transceivers are reported in this paper, confirming both the accuracy and the efficiency of the proposed framework.

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Constructive Signal Approximations for Fast Transient Simulation of Coupled Channels

This paper presents an improved algorithm for small cell (SCs) deployment in the heterogeneous network (HetNet) future generations of mobile networks. The sequential and fixed number of the SCs deployment is formulated as a joint optimization of load balancing and interference (JOLBI) minimization over the number and locations of the distributed user equipment (UE) forming a hotspot (HS). Then, the SCs are adaptively powered ON or OFF according to outcomes of the proposed clustering algorithms applied to the UEs' distribution. The conceived integrated solution of the JOBLI and clustering algorithm does not only satisfy the coverage constraint and maximize the minimum user throughput of the HetNet, but also enables an energy effective SCs deployment. The simulation results show that this JOLBI and clustering algorithm enables a power saving of the whole network by 35% when HS of UEs are considered in the network simulations.

Dynamic Clustering for Power Effective Small Cell Deployment in HetNet 5G Networks

This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the Newton-Neville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good prediction accuracy of the time domain voltage and current waveforms as well as the eye diagram of the high-speed communication I/O link while speeding-up the transient simulation compared to the transistor level model.

/pdf/power-supply-and-temperature-aware-i-o-buffer-model-for-xxq4fg0da4.pdf

Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation

This paper presents an assessment of jitter induced by power and ground (P/G) voltage variations. The assessment is based on an extended input/output buffer information specification (IBIS)-like model for capturing the effect of P/G signal variations under simultaneous switching output buffers. The implemented large signal equivalent-circuit model is validated under different test conditions having different P/G voltage variations for predicting the output signal distortions. The associated jitter analysis by predicting the eye diagram under the noise conditions is performed. The maximum prediction error for the peak to peak values of eye jitter and eye height are 7.06% and 2.59%, respectively.

I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO)

This paper investigates two-coil inductive channel for an efficient Wireless Power Transfer (WPT), while intelligently enabling high-data rate communication. The analysis is based on the power efficiency and channel capacity performance, which are determined based on the multiport scattering (S)-parameters numerical simulation results, using a lumped equivalent circuit model. Different access points and configuration scenarios, along with the decoupling filters design consideration of power and data links, were compared in order to cognitively share the two-coil inductive channel, for handling both high-power signal and low-power modulated high- frequency data signal. The performance of the transmission and isolation between the power and data link is evaluated. The theoretical channel capacity of the proposed two-coil circuit is calculated, as a function of the coupling coefficient k12, as well as in the presence of an additive white Gaussian noise and signal to noise ratio. This paper adds to the intelligence and cognition of the radio, to efficiently use the limited available spectrum for broadband communications, in addition to power transmission, simultaneously.

Malek Souilem

Papers

Dynamic Clustering for Power Effective Small Cell Deployment in HetNet 5G Networks

An IBIS-like Modelling for Power/Ground Noise Induced Jitter under Simultaneous Switching Outputs (SSO)

Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation

I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO)

Wireless Power Transfer and Data Communication Cognitive Radio through Two-Coil Inductive Channel