Mandar S. Bhoir

Bio: Mandar S. Bhoir is an academic researcher from Indian Institute of Technology Gandhinagar. The author has contributed to research in topics: Transistor & MOSFET. The author has an hindex of 3, co-authored 11 publications receiving 26 citations.

Source Underlap—A Novel Technique to Improve Safe Operating Area and Output-Conductance in LDMOS Transistors

Abstract: In this article, we have proposed a simple, novel, and cost-effective technique to mitigate the ON-state performance issues in laterally diffused MOS (LDMOS) transistors. We propose a novel technique-LDMOS transistor with source-side underlap (SU), which can be integrated into any existing LDMOS/bipolar-CMOS-DMOS (BCD) process flow without any additional processing/area cost. Unlike commonly used solutions, the SU LDMOS provides flexibility to improve ON-state behavior without disturbing other performance metrics. The proposed SU LDMOS transistor is experimentally demonstrated using 180-nm CMOS technology, and noteworthy improvement in ON-state breakdown voltage, electrical safe operating area (SOA), output conductance, transistor intrinsic gain, and cutoff frequency is reported. The physics behind the improvement is also discussed in detail.

Variability sources in nanoscale bulk FinFETs and TiTaN- a promising low variability WFM for 7/5nm CMOS nodes

Abstract: A systematic methodology to segregate different variability sources from electrical measurements, in sub-10nm W fin FinFETs, is proposed. The threshold voltage variation, coming from gate-metal work-function and oxide charge variations, is shown to be the major contributor to in-wafer variability. The contribution of FER, GER and RDF to V t variability is negligible. TiTaN, a new work function metal (WFM) for the metal gate-stack, is introduced and it provides ~37% less total and ~27% less random variability.

Predictive effective mobility model for FDSOI transistors using technology parameters

Abstract: by Pragya Kushwaha, Harshit Agarwal, Mandar Bhoir, Nihar R. Mohapatra, Sourabh Khandelwal, Juan Pablo Duarte, Yen-Kai Lin, Huan-Lin Chang, Chenming hu and Yogesh Singh Chauhan

Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis

Abstract: This paper discusses in detail the effects of Sub-10nm fin-width ( $\text{W}_{fin}$ ) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the trans-conductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm $\text{W}_{fin}$ regime, cannot be improved just by $\text{W}_{fin}$ scaling but by optimizing source/drain resistance, gate dielectric thickness together with the $\text{W}_{fin}$ scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.

Effects of Scaling on Analog FoMs of UTBB FD-SOI MOS Transistors: A Detailed Analysis

Abstract: In this article, the combined effect of BOX thickness ( ${T}_{\text {BOX}}$ ) and ground-plane (GP) doping ( ${N}_{\text {GP}}$ ) on channel carrier mobility and analog figures of merit (FoMs) is investigated It is reported that the thin BOX along with higher ${N}_{\text {GP}}$ will limit the electron/hole mobility of ultrathin body and BOX fully depleted silicon-on-insulator (UTBB FD-SOI) MOS transistors The physics responsible for this observation is discussed in detail The contrasting behavior of different GPs, the effect of ${T}_{\text {BOX}}$ scaling, and gate-length scaling on device behavior is also analyzed It is also shown that in advanced UTBB FD-SOI MOS transistors, a tradeoff exists between transistor intrinsic gain, cutoff frequency, and non-linearity In nMOS transistors, the best intrinsic gain and cut-off frequency can be achieved with ultrathin BOX and n-type GP (or with no GP), whereas the best linearity can be achieved with ultrathin BOX and p-type GP implant

Transistors based on two-dimensional materials for future integrated circuits

Abstract: Field-effect transistors based on two-dimensional (2D) materials have the potential to be used in very large-scale integration (VLSI) technology, but whether they can be used at the front end of line or at the back end of line through monolithic or heterogeneous integration remains to be determined. To achieve this, multiple challenges must be overcome, including reducing the contact resistance, developing stable and controllable doping schemes, advancing mobility engineering and improving high-κ dielectric integration. The large-area growth of uniform 2D layers is also required to ensure low defect density, low device-to-device variation and clean interfaces. Here we review the development of 2D field-effect transistors for use in future VLSI technologies. We consider the key performance indicators for aggressively scaled 2D transistors and discuss how these should be extracted and reported. We also highlight potential applications of 2D transistors in conventional micro/nanoelectronics, neuromorphic computing, advanced sensing, data storage and future interconnect technologies. This Review examines the development of field-effect transistors based on two-dimensional materials and considers the challenges that need to be addressed for the devices to be incorporated into very large-scale integration (VLSI) technology.

Benchmarking monolayer MoS2 and WS2 field-effect transistors.

Abstract: Here we benchmark device-to-device variation in field-effect transistors (FETs) based on monolayer MoS2 and WS2 films grown using metal-organic chemical vapor deposition process. Our study involves 230 MoS2 FETs and 160 WS2 FETs with channel lengths ranging from 5 μm down to 100 nm. We use statistical measures to evaluate key FET performance indicators for benchmarking these two-dimensional (2D) transition metal dichalcogenide (TMD) monolayers against existing literature as well as ultra-thin body Si FETs. Our results show consistent performance of 2D FETs across 1 × 1 cm2 chips owing to high quality and uniform growth of these TMDs followed by clean transfer onto device substrates. We are able to demonstrate record high carrier mobility of 33 cm2 V−1 s−1 in WS2 FETs, which is a 1.5X improvement compared to the best reported in the literature. Our experimental demonstrations confirm the technological viability of 2D FETs in future integrated circuits. Here, the authors perform a benchmark study of field-effect transistors (FETs) based on 2D transition metal dichalcogenides, i.e., 230 MoS2 and 160 WS2 FETs, and track device-to-device variations to gauge the technological viability in future integrated circuits.

An Effective Method to Compensate Total Ionizing Dose-Induced Degradation on Double-SOI Structure

Abstract: The existence of buried oxide (BOX) layer and the strong coupling effect between the front and back channels can worsen the radiation-induced degradation on fully depleted silicon-on-insulator (FDSOI) device. To mitigate the radiation impact, a new structure named double SOI is introduced in this paper. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the BOX layer. With this structure, FDSOI device parameter degradation due to total dose is studied, and some abnormal phenomena, such as the transconductance hump and the mobility enhancement, are observed and discussed. Sentaurus TCAD simulations are used for further analysis. Moreover, the impact of negative back-gate bias to transistor parameter degradation is investigated, and an improved back-gate compensation strategy is proposed. Technology improvement such as thinning the BOX on total ionizing dose (TID) amelioration is also discussed with TCAD simulation.

Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect

Abstract: In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases.