다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

International Journal of Computer and Applications

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

A geometric program (GP) is a type of mathematical optimization problem characterized by objective and constraint functions that have a special form. Recently developed solution methods can solve even large-scale GPs extremely efficiently and reliably; at the same time a number of practical problems, particularly in circuit design, have been found to be equivalent to (or well approximated by) GPs. Putting these two together, we get effective solutions for the practical problems. The basic approach in GP modeling is to attempt to express a practical problem, such as an engineering analysis or design problem, in GP format. In the best case, this formulation is exact; when this is not possible, we settle for an approximate formulation. This tutorial paper collects together in one place the basic background material needed to do GP modeling. We start with the basic definitions and facts, and some methods used to transform problems into GP format. We show how to recognize functions and problems compatible with GP, and how to approximate functions or data in a form compatible with GP (when this is possible). We give some simple and representative examples, and also describe some common extensions of GP, along with methods for solving (or approximately solving) them.

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A tutorial on geometric programming

A fusion-based enhancing method for weakly illuminated images

Shrinking in the device dimensions increases the device density on the chip and thus reducing the overall chip area requirement for logic implementation Minimising the chip area is not a lonely optimisation performance factor for a VLSI chip designer The other equally important performance parameters such that power dissipation and propagation delay are the thinkable facts for a designer The focusable part of power dissipation is the huge leakage current in deep submicron (DSM) regime Many leakage reduction techniques are applied to reduce the leakage current in the DSM regime but they have own limitations Our proposed on/off logic (ONOFIC) approach gives an excellent settlement between power dissipation and propagation delay for designing the nanoscale CMOS circuits It uses extra insertion of two transistors (an NMOS and a PMOS) within the logic block The exact on/off level of the ONOFIC block improves the power dissipation and propagation delay of the logic circuits In this article, ONOFIC appro

ONOFIC approach: low power high speed nanoscale VLSI circuits design

In this paper, latch free clock gating techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and 55.78% of total dynamic power when device operating frequency is 100MHz, 1GHz, 10GHz, 100GHz and 1 THz. After implementation of clock gating techniques in ALU, Clock power reduces to 17.85%, 23.39%, 26.49% and 27.19% of total dynamic power, when device operating frequency is 1GHz, 10GHz, 100GHz and 1 THz. On 1 THz operating frequency, when we use clock gating, there are 72.77% reduction in clock power, 38.88% reduction in IOs power and 44% reduction in dynamic power in compare to power consumption without using clock gating techniques. Target device is 90-nm Spartan-3. There is 14.57% reduction in junction temperature on 10GHz operating frequency in compare to temperature without using clock gating techniques. Clock gating saves power but increases over all area. There is 32.35%, 37.84%, 43.31% and 44% reduction in dynamic current when we use clock gate on 1GHz, 10GHz, 100GHz and 1THz operating frequency respectively.

Clock gating based energy efficient ALU design and implementation on FPGA

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the l...

INDEP approach for leakage reduction in nanoscale CMOS circuits

In this work, our focus is on study and analysis of various clock gating technique and design and analysis of clock gating based low power sequential circuit at RTL level. Virtex-6 is 40-nm FPGA, on which we implement our circuit to re-assure power reduction in sequential circuit. Clock gating is implemented on smaller circuit called D flip-flop and on larger circuit called 16-bit register. The percentage of reduction in dynamic power especially clock power is verified for different device operating frequency. Here, we achieved 87.09%, 88.02%, 88.02%, and 88.01% clock power reduction in this work when clock period is 1ns, 0.1ns, 0.01ns and 0.001ns respectively. Design and implementation result shows that there is reduction in dynamic power especialy significant reduction in clock power We also achieved 15%, 14.22%, 14.58%, 14.57% and 14.57% dynamic power reduction when clock period is 10ns, 1ns, 0.1ns, 0.01ns, and 01ps respectively.

Manisha Pattanaik

Papers

ONOFIC approach: low power high speed nanoscale VLSI circuits design

Clock gating based energy efficient ALU design and implementation on FPGA

INDEP approach for leakage reduction in nanoscale CMOS circuits

Clock gated low power sequential circuit design

Histogram statistics based variance controlled adaptive threshold in anisotropic diffusion for low contrast image enhancement