Manoj Khanna

Bio: Manoj Khanna is an academic researcher from University of Delhi. The author has contributed to research in topics: Threshold voltage & MOSFET. The author has an hindex of 5, co-authored 25 publications receiving 91 citations. Previous affiliations of Manoj Khanna include Ramjas College.

Analytical two-dimensional modeling for potential distribution and threshold voltage of the short-channel fully depleted SOI (silicon-on-insulator) MOSFET

Abstract: A two-dimensional analytical model for fully depleted SOI MOSFETs is presented. An extensive study of potential distribution in the silicon film is carried out for non-uniform doping distribution and extended to find an expression for threshold voltage in the sub micrometer region. The results so obtained are verified with experimental data. The present model calculates a critical gate voltage (for short channel fully depleted SOI devices) beyond which gate losses its control on drain current. The advantages of SOI MOSFETs over the bulk counterparts are explained on the basis of drain induced barrier lowering [DIBL]. It is also shown that the threshold voltage for the thin film SOI MOSFET is less than that of bulk MOSFET. The short-channel effects, DIBL and threshold voltage reduction, are well predicted in the present model.

Microwave monolithic filter and phase shifter using magnetic nanostructures

Abstract: Monolithic Microwave Integrated Circuit (MMIC) have major impact on the development of microwave communication technology. Transition metal based ferromagnetic nano-wired (FMNWs) substrate are of special interest in order to fabricate these MMIC devices. Their saturation magnetization is comparatively higher than ferrites which makes them suitable for high frequency (>10 ∼ 40 GHz) operation at zero or a small applied magnetic field. The CoFeB nanowires in anodic alumina templates were synthesized using three-electrode electro-deposition system. After electro-deposition, 1μm thick Cu layer was sputtered on the top surface of FMNW substrate and lithography was done to design microstrip lines. These microstrip transmission lines were tested for band-stop filters and phase shifters based on ferromagnetic resonance (FMR) over a wide applied magnetic field (H) range. It was observed that attenuation and frequency increase with the increase of magnetic field (upto 5.3 kOe). For phase shifter, the influence of magnetic material was studied for two frequency regions: (i) below FMR and (ii) above FMR. These two frequency regions were suitable for many practical device applications as the insertion loss was very less in these regions in comparison to resonance frequency regions. In the high frequency region (at 35 GHz), the optimal differential phase shift increased significantly to ∼ 250 deg/cm and around low frequency region (at 24 GHz), the optimal differential phase shift is ∼175 deg/cm at the highest field (H) value.

Nanoscale field-effect transistors: An ultimate size analysis

Abstract: We have used a simple, analytically solvable model to analyze the characteristics of dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with 10 nm-scale channel length L. The model assumes ballistic dynamics of two-dimensional electrons in an undoped channel between highly doped source and drain. When applied to silicon n-MOSFETs, calculations show that the voltage gain (necessary for logic applications) drops sharply at L∼10 nm, while the conductance modulation remains sufficient for memory applications until L∼4 nm.

On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs

Abstract: The authors study the dependence of the performance of silicon-on-insulator (SOI) Schottky-barrier (SB) MOSFETs on the SOI body thickness and show a performance improvement for decreasing SOI thickness. The inverse subthreshold slopes S extracted from the experiments are compared with simulations and an analytical approximation. Excellent agreement between experiment, simulation, and analytical approximation is found, which shows that S scales approximately as the square root of the gate oxide and the SOI thickness. In addition, the authors study the impact of the SOI thickness on the variation of the threshold voltage Vth of SOI SB-MOSFETs and find a nonmonotonic behavior of Vth. The results show that to avoid large threshold voltage variations and achieve high-performance devices, the gate oxide thickness should be as small as possible, and the SOI thickness should be ~ 3 nm

Deep submicrometer double-gate fully-depleted SOI PMOS devices: a concise short-channel effect threshold voltage model using a quasi-2D approach

Abstract: This paper reports a concise short-channel effect threshold voltage model using a quasi-2D approach for deep submicrometer double-gate fully-depleted SOI PMOS devices. By considering the hole density at the front and the back channels simultaneously, the analytical threshold voltage model provides an accurate prediction of the short-channel threshold voltage behavior of the deep submicrometer double-gate fully-depleted SOI PMOS devices as verified by 2D simulation results. The analytical short-channel effect threshold voltage model can also be useful for SOI NMOS devices.