Marco Zanuso

Bio: Marco Zanuso is an academic researcher from Qualcomm. The author has contributed to research in topics: Phase-locked loop & Phase noise. The author has an hindex of 10, co-authored 27 publications receiving 618 citations. Previous affiliations of Marco Zanuso include Polytechnic University of Milan.

A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- ${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5-mW Power

Abstract: This paper introduces a ΔΣ fractional-N digital PLL based on a single-bit TDC. A digital-to-time converter, placed in the feedback path, cancels out the quantization noise introduced by the dithering of the frequency divider modulus and permits to achieve low noise at low power. The PLL is implemented in a standard 65-nm CMOS process. It achieves - 102-dBc/Hz phase noise at 50-kHz offset and a total absolute jitter below 560 fsrms (integrated from 3 kHz to 30 MHz), even in the worst-case of a -42-dBc in-band fractional spur. The synthesizer tuning range spans from 2.92 GHz to 4.05 GHz with 70-Hz resolution. The total power consumption is 4.5 mW, which leads to the best jitter-power trade-off obtained with a fractional-N synthesizer. The synthesizer demonstrates the capability of frequency modulation up to 1.25-Mb/s data rate.

Noise Analysis and Minimization in Bang-Bang Digital PLLs

Abstract: In digital bang-bang phase-locked loops (BBPLLs), both the hard nonlinearity of the phase detector and the frequency granularity of the digitally controlled oscillator (DCO) can give rise to undesired tones or peaking in the output spectrum. This work derives the maximum ratio between DCO resolution and jitter, which avoids limit cycles, in the case of dominant DCO noise over reference noise. Moreover, the output jitter is expressed in closed form as a function of the loop parameters and latency, revealing the existence of a minimum and suggesting an optimum design criterion. Finally, an estimation of the BBPLL output spectrum taking into account the quantization noise is provided.

A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation

Abstract: A digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented which is able to achieve wide loop bandwidth while producing low fractional spurs. The loop adopts a fractional-N divider based on a phase interpolator, allowing to shrink the TDC dynamic range and to improve its linearity. A dynamic-element matching algorithm is employed to further improve TDC linearity and an original correlation algorithm is used to correct for the phase interpolator mismatches. Both digital algorithms operate in background and they are demonstrated to be concurrently effective in reducing in-band fractional spurs below -57 dBc. The circuit is fully integrated in a 65 nm CMOS process and it synthesizes a carrier in the 3.0-3.6 GHz range from a 40 MHz crystal reference with 40 Hz resolution. It achieves -104-dBc/Hz phase noise at 400-kHz offset and a 3.2-MHz maximum loop bandwidth. The synthesizer dissipates 80 mW and occupies 0.4 mm2.

Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL

Abstract: This paper presents the design of a time-to-digital converter (TDC) suitable for a 3.5-GHz all-digital phase-lock loop (PLL). The converter is based on a digital bang-bang delay-lock loop, which allows constant resolution over process and temperatures spreads, avoids an off-chip filter and guarantees fast lock. The clock rate of the digital filter is scaled down by eight from the 3.5-GHz input to allow its implementation with standard cells. The occurrence of a limit cycle is analytically predicted and properly minimized, and its effect on the PLL phase noise is discussed. The circuit fabricated in 90-nm CMOS entails 16 delay stages, which lock to the input frequency in the 2.9-3.9-GHz range (limited by the available signal source). The delay of each TDC cell can be controlled with 50-fs step and the TDC time resolution is 16 ps at 3.9 GHz. The power consumption ranges between 8.1 and 16.5 mW, respectively. The limit-cycle-induced spur is below - 50 dBc. The area occupation is 0.032 mm2.

Quantization Effects in All-Digital Phase-Locked Loops

Abstract: This brief analyzes the impact of the quantization noise sources in all-digital phase-locked loops (ADPLLs), recently employed as frequency synthesizers. In general, the in-band phase noise is not only caused by the phase quantization of the time-to-digital converter, but also by the frequency quantization of the digitally controlled oscillator (DCO). The delta-sigma modulator placed at the DCO input refines the frequency quantization and adds another source of in-band PLL noise. Interestingly, the higher the modulator order, the higher this source of in-band phase noise. A method for the estimation of all the quantization noise contributors is provided, which is proven by mixed-mode simulations.

A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- ${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5-mW Power

Abstract: This paper introduces a ΔΣ fractional-N digital PLL based on a single-bit TDC. A digital-to-time converter, placed in the feedback path, cancels out the quantization noise introduced by the dithering of the frequency divider modulus and permits to achieve low noise at low power. The PLL is implemented in a standard 65-nm CMOS process. It achieves - 102-dBc/Hz phase noise at 50-kHz offset and a total absolute jitter below 560 fsrms (integrated from 3 kHz to 30 MHz), even in the worst-case of a -42-dBc in-band fractional spur. The synthesizer tuning range spans from 2.92 GHz to 4.05 GHz with 70-Hz resolution. The total power consumption is 4.5 mW, which leads to the best jitter-power trade-off obtained with a fractional-N synthesizer. The synthesizer demonstrates the capability of frequency modulation up to 1.25-Mb/s data rate.

A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation

Abstract: This paper presents a time-to-digital converter (TDC) architecture capable of reaching high-precision and high-linearity with moderate area occupation per measurement channel. The architecture is based on a coarse counter and a couple of two-stage interpolators that exploit the cyclic sliding scale technique in order to improve the conversion linearity. The interpolators are based on a new coarse-fine synchronization circuit and a new single-stage Vernier delay loop fine interpolation. In a standard cost-effective 0.35 μm CMOS technology the TDC reaches a dynamic range of 160 ns, 17.2 ps precision and differential non-linearity better than 0.9% LSB rms. The TDC building block was designed in order to be easily assembled in a multi-channel monolithic TDC chip. Coupled with a SPAD photodetector it is aimed for TCSPC applications (like FLIM, FCS, FRET) and direct ToF 3-D ranging.

A Digital PLL With a Stochastic Time-to-Digital Converter

Abstract: A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits the stochastic properties of a set of latches to achieve high resolution. A prototype DPLL test chip has been fabricated in a 0.13-mum CMOS process, features a 0.7-1.7-GHz oscillator tuning range and a 6.9-ps rms jitter, and consumes 17 mW under 1.2-V supply while operating at 1.2 GHz.

A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators

Abstract: In this paper, we propose a method to reduce a flicker (1/f) noise upconversion in voltage-biased RF oscillators. Excited by a harmonically rich tank current, a typical oscillation voltage waveform is observed to have asymmetric rise and fall times due to even-order current harmonics flowing into the capacitive part, as it presents the lowest impedance path. The asymmetric oscillation waveform results in an effective impulse sensitivity function of a nonzero dc value, which facilitates the 1/f noise upconversion into the oscillator’s 1/f3 phase noise. We demonstrate that if the $\omega _{0}$ tank exhibits an auxiliary resonance at 2 $\omega _{0}$ , thereby forcing this current harmonic to flow into the equivalent resistance of the 2 $\omega _{0}$ resonance, then the oscillation waveform would be symmetric and the flicker noise upconversion would be largely suppressed. The auxiliary resonance is realized at no extra silicon area in both inductor- and transformer-based tanks by exploiting different behaviors of inductors and transformers in differential- and common-mode excitations. These tanks are ultimately employed in designing modified class-D and class-F oscillators in 40 nm CMOS technology. They exhibit an average flicker noise corner of less than 100 kHz.

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

Abstract: A digital fractional-N PLL that employs a high resolution TDC and a truly $\Delta \Sigma$ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out $\Delta \Sigma$ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution. By using TA-TDC in place of a BBPD, the limit cycle behavior that plagues BB-PLLs is greatly suppressed by the TA-TDC, thus permitting wide PLL bandwidth. The proposed architecture is also less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL. Fabricated in 65 nm CMOS process, the prototype PLL achieves better than ${-}$ 106 dBc/Hz in-band noise and 3 MHz PLL bandwidth at 4.5 GHz output frequency using 50 MHz reference. The PLL consumes 3.7 mW and achieves better than 490 fs $ _{{\rm rms}}$ integrated jitter. This translates to a FoM $ _{{\rm J}}$ of ${-}$ 240.5 dB, which is the best among the reported fractional-N PLLs.