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Author

Marcus Ray

Other affiliations: Motorola
Bio: Marcus Ray is an academic researcher from Freescale Semiconductor. The author has contributed to research in topics: Field-effect transistor & Layer (electronics). The author has an hindex of 7, co-authored 11 publications receiving 266 citations. Previous affiliations of Marcus Ray include Motorola.

Papers
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Patent
09 Jan 2003
TL;DR: An implant-free enhancement mode metal-oxide semiconductor field effect transistor (EMOSFET) was proposed in this article, where an epitaxial material layer has a channel layer and at least one doped layer.
Abstract: An implant-free enhancement mode metal-oxide semiconductor field effect transistor (EMOSFET) is provided. The EMOSFET has a III-V compound semiconductor substrate and an epitaxial layer structure overlying the III-V compound semiconductor substrate. The epitaxial material layer has a channel layer and at least one doped layer. A gate oxide layer overlies the epitaxial layer structure. The EMOSFET further includes a metal gate electrode overlying the gate oxide layer and source and drain ohmic contacts overlying the epitaxial layer structure.

68 citations

Patent
10 Nov 2005
TL;DR: In this article, an integrated coupler is proposed to provide efficient and reproducible RF coupling without increasing the die footprint of the RF circuit, and the coupler can be used in the same substrate using the same IPD process technology.
Abstract: A radio frequency ('RF') (100) circuit configured in accordance with an embodiment of the invention is fabricated on a substrate using integrated passive device ('IPD') process technology. The RF circuit (100) (which may be, for example, a harmonic filter) includes at least one RF signal line section (204) and an integrated RF coupler (304) located proximate to the RF signal line section. The integrated RF coupler (304), its output (212) and grounding contact pads (210), and its matching network (208) are fabricated on the same substrate using the same IPD process technology. The integrated RF coupler provides efficient and reproducible RF coupling without increasing the die footprint of the RF circuit.

66 citations

Journal ArticleDOI
Lianjun Liu1, Shun-Meen Kuo1, J. Abrokwah1, Marcus Ray1, D. Maurer1, M. Miller1 
TL;DR: In this paper, an integrated passive device (IPD) technology has been developed to meet the ever increasing needs of size and cost reduction in radio front-end transceiver module applications, which includes a thick plated gold metal process to reduce resistive loss; MIM capacitors using PECVD SiN dielectric layer; airbridges for inductor underpass and capacitor pick-up; and a 10 mil finished GaAs substrate to improve inductor quality factor.
Abstract: An integrated passive device (IPD) technology has been developed to meet the ever increasing needs of size and cost reduction in radio front-end transceiver module applications. Electromagnetic (EM) simulation was used extensively in the design of the process technology and the optimization of inductor and harmonic filter designs and layouts. Parameters such as inductor shape, inner diameter, metal thickness, metal width, and substrate thickness have been optimized to provide inductors with high quality factors. The technology includes 1) a thick plated gold metal process to reduce resistive loss; 2) MIM capacitors using PECVD SiN dielectric layer; 3) airbridges for inductor underpass and capacitor pick-up; and 4) a 10 mil finished GaAs substrate to improve inductor quality factor. Both lumped element circuit simulations and electromagnetic (EM) simulations have been used in the harmonic filter circuit designs for high accuracy and fast design cycle time. This paper will present the EM simulation calibration and demonstrate the importance of using EM simulation in the filter design in order to achieve first-time success in wafer fabrication. The fabricated IPD devices have insertion loss of 0.5 dB and harmonic rejections of 30dB with die size of 1.42 mm for high band (1710 MHz-1910 MHz) and 1.89 mm for low band (824-915 MHz) harmonic filters.

44 citations

Proceedings ArticleDOI
Lianjun Liu1, Shun-Meen Kuo1, J. Abrokwah1, Marcus Ray1, D. Maurer1, M. Miller1 
20 Jun 2005
TL;DR: In this paper, an integrated passive device (IPD) on GaAs technology has been developed to meet the ever increasing needs of size and cost reduction in radio transmit module applications, which includes the following features: 1) thick plated gold metal process to reduce resistive loss; 2) MIM capacitors using PECVD Si/sub 3/N/sub 4/ dielectric layer; 3) airbridges for inductor underpass and capacitor pick-up; and 4) 10mil finished GaAs substrate.
Abstract: An integrated passive device (IPD) on GaAs technology has been developed to meet the ever increasing needs of size and cost reduction in radio transmit module applications. Extensive electromagnetic (EM) simulations were used in the design of process technology and the optimization of inductor and harmonic filters design and layout. Parameters such as inductor shape, inner diameter, metal thickness, metal width and substrate thickness have been optimized to provide inductors with high quality factors. The technology includes the following features: 1) thick plated gold metal process to reduce resistive loss; 2) MIM capacitors using PECVD Si/sub 3/N/sub 4/ dielectric layer; 3) airbridges for inductor underpass and capacitor pick-up; and 4) 10mil finished GaAs substrate to improve inductor quality factor. Both lumped element circuit simulation and electromagnetic (EM) simulations have been used in the harmonic filter circuit design for fast design cycle time and high accuracy. This paper presents the EM simulation calibration and demonstrate the importance of using EM simulations in filter design in order to achieve success in first wafer fabrication. The fabricated IPD devices have insertion loss of 30dB with die size of 1.42mm/sup 2/ for high band (1710MHz -1910MHz) and 1.89mm/sup 2/ for low band (824MHz-915MHz) harmonic filters.

36 citations

Patent
03 Aug 2007
TL;DR: In this article, the harmonic termination circuit of a transceiver includes a variable capacitor that is capable of adjusting its capacitance in response to the tunable harmonic termination voltage to achieve at least two modes of operation.
Abstract: A transceiver includes a harmonic termination circuit that receives a tunable harmonic voltage from a power amplifier control. The harmonic termination circuit includes a variable capacitor that is capable of adjusting its capacitance in response to the tunable harmonic termination voltage to achieve at least two modes of operation. The at least two modes of operation may be EDGE mode and GSM mode. In this embodiment, the harmonic termination circuit allows for linearity specifications of EDGE to be met, while not degrading the efficiency of the transceiver when operating in GSM mode. In one embodiment, the harmonic termination circuit further includes an inductive element in series with the variable capacitor.

16 citations


Cited by
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Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

Patent
15 Sep 2010
TL;DR: In this paper, the Deeply Depleted Channel (DDC) transistors are used to reduce power consumption in devices by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as broader electronics industry to avoid a costly and risky switch to alternative technologies.
Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

193 citations

Patent
07 Jul 2006
TL;DR: In this paper, negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device, either before or after formation of the negative ion regions.
Abstract: A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region.

145 citations

Patent
Scott T. Sheppard1
19 Jul 2006
TL;DR: In this paper, a switch mode power amplifier and a field effect transistor are described for use in a switchmode power amplifier with a gate terminal positioned on a dielectric material.
Abstract: Disclosed are a switch mode power amplifier and a field effect transistor especially suitable for use in a switch mode power amplifier. The transistor is preferably a compound high electron mobility transistor (HEMT) having a source terminal and a drain terminal with a gate terminal therebetween and positioned on a dielectric material. A field plate extends from the gate terminal over at least two layers of dielectric material towards the drain. The dielectric layers preferably comprise silicon oxide and silicon nitride. A third layer of silicon oxide can be provided with the layer of silicon nitride being positioned between layers of silicon oxide. Etch selectivity is utilized in etching recesses for the gate terminal.

118 citations

Patent
20 Oct 2008
TL;DR: In this paper, a trap-rich layer, such as a polycrystalline Silicon layer over a semiconductor substrate, is used to substantially immobilize a surface conduction layer at the surface of the semiconductor substrategies at radio frequency (RF) frequencies.
Abstract: The present invention relates to using a trap-rich layer, such as a polycrystalline Silicon layer, over a semiconductor substrate to substantially immobilize a surface conduction layer at the surface of the semiconductor substrate at radio frequency (RF) frequencies. The trap-rich layer may have a high density of traps that trap carriers from the surface conduction layer. The average release time from the traps may be longer than the period of any present RF signals, thereby effectively immobilizing the surface conduction layer, which may substantially prevent capacitance and inductance changes due to the RF signals. Therefore, harmonic distortion of the RF signals may be significantly reduced or eliminated. The semiconductor substrate may be a Silicon substrate, a Gallium Arsenide substrate, or another substrate.

89 citations